9.2.1.2 Detailed Design Procedure

One of the channels of the OPA2834 is connected to the shunt resistor in Figure 56 in a 20-V/V difference amplifier configuration. Equation 3 gives the gain of this circuit. A well-known way to start the design of this signal chain is to start from fixating the value of R_G.

Equation 3.

where

• R_F and R_G are the feedback and gain resistors for channel A of the OPA2834

The values of R_F and R_G depend on multiple factors. Using small resistors in the feedback network helps reduce output noise and improves measurement accuracy. Small feedback resistors result in larger power dissipation in the amplifier output stage. In order to reduce this power dissipation, large-value resistors reduce the phase margin and cause gain peaking; see Figure 47. Select the values of R_F and R_G from the recommended range of values for this device. As given in Equation 4, care must be taken to use a gain-resistor value large enough to limit the current through the input ESD diodes to within 10 mA for a 10-V input transient (as per the design targets) with the amplifier powered off a 5-V supply.

Equation 4.

where

• V_IN is the input transient voltage
• V_D is the ESD diode forward voltage drop
• I_D is the current resulting from this input transient flowing through the ESD diode

A total gain of 20 V/V is required from the amplifier signal chain. We have chosen R_G = 500 Ω in this design, thus R_F = 10 kΩ. A SAR ADC features a sampling capacitor at the input pin. At the end of every conversion cycle, the circuit driving this SAR ADC needs to replenish this capacitor. Using the analog calculator, the required bandwidth for the amplifier to drive the ADS7056 ( sampling rate of 1MSPS and a clock frequency of 40 MHz ) comes out to be at least 5 MHz. Because of this requirement, the two amplifier channels are configured in gains of 20 V/V and 1 V/V, respectively. The effective bandwidth of the amplifier set in a gain on 20 V/V comes out to be 20MHz/20 = 1MHz. The bandwidth of the second amplifier set in a gain of 1V/V , equals 50MHz. Thus the rise time and the settling time of the entire signal chain is decided by the first amplifier. Using an amplifier in the first stage of any lower bandwidth will result in a penalty in the settling time on the ADC. The 1.24-V reference voltage to the noninverting input of channel 1 sets the output common-mode voltage to 1.24 V. The two channels of the OPA2834 together provide a signal gain of 20 V/V. The first Amplifier's bandwidth is dedicated to gaining up the signal with a very low rise time whereas the function of the second amplifier is to utilize its bandwidth to drive the SAR ADC to achieve the required settling.

The ADS7056 samples at 1 MSPS with a 40-MHz clock which translates to an acquisition time of 550 nsec. This provides the dual amplifier 550 nsec to settle to the required accuracy. In this application, we target an accuracy of 0.1%. As the ADC is powered from a 3.3 V supply we have assumed the full scale to be 3 V.

An accuracy of 0.1% of 3 V = 3 mV. Thus the second OPA2834 should settle to ±3 mV of its final intended value within 550 nsec. Figure 57 shows the TINA simulation plots for the OPA2834 driving the ADS7056. Input voltage (red) is the signal swing across the shunt resistance, the error signal is the % error in the voltage across the sampling capacitor from its steady-state value (instantaneous value - final value). The input signal sharply transits from its lowermost point to the uppermost point at 600 nsec instant. This can be considered as a short circuit event or step increase due to a mosfet switching in real-world circuits. This acquisition window of the ADC as discussed earlier is 550 nsec. The details on how this time is decided by the ADC can be found from the ADS7056 datasheet. Thus the % error signal (blue) must settle down to less than 0.1 % before the end of this 550 nsec window. The output signal (black) is divided by 20 V/V so as to be shown beside its corresponding input signal. As per Figure 57 the error signal comfortably settles to the final value with an error % of -0.05% which is well within the 0.1% accuracy. Hence the dual OPA2834 settles to 0.1% accuracy within 550 ns with a worst-case, 0 to 3-V full-scale transient output that too in a gain configuration of 20 V/V as shown in the Figure 57. OPA2834 enables single sample settling for ADS7056 running at 40 MHz clock with 1 MSPS.

Figure 57. OPA2834 Settling Performance With the ADS7056

Another way to look at the signal chain is using the SNR and THD numbers. A 2 kHz tone is input to the first OPA2834 shown in Figure 56. This signal is gained up by 20 V/V and fed to the ADS7056. The results are compared to the specifications given in the ADS7056 datasheet.

Using a slower clock with the ADC and the same sampling rate causes the ENOB to reduce as the amplifier has reduced time available to settle. This reduction in ENOB is restored with a lower sampling frequency or use of wider bandwidth amplifiers from the OPA83x family of products.