at T_A = 25°C, V_S = 5.5 V, R_L = 10 kΩ connected to V_S / 2, V_CM = V_S / 2, and V_OUT = V_S / 2 (unless otherwise noted)

Figure 7-1 Offset Voltage Production Distribution

Figure 7-3 Offset Voltage vs Temperature

Figure 7-5 Offset Voltage vs Common-Mode Voltage

Figure 7-7 I_B and I_OS vs Common-Mode Voltage

CL = 10 pF

Figure 7-9 Open-Loop Gain and Phase vs Frequency

Figure 7-11 V_O vs I Sourcing and Sinking

Figure 7-13 CMRR vs Frequency (Referred to Input)

Figure 7-15 0.1-Hz to 10-Hz Flicker Noise

VS = 5.5 V		VICM = 2.5 V	RL = 2 kΩ
Gain = 1		BW = 80 kHz	VOUT = 0.5 Vrms

Figure 7-17 THD + N vs Frequency

VS = 5.5 V				VICM = 2.5 V	BW = 80 kHz
VOUT = 0.5 Vrms

Figure 7-19 THD + N vs Amplitude

Figure 7-21 Quiescent Current vs Temperature

Figure 7-23 Open-Loop Gain vs Output Voltage

VS = 5.5 V	VICM = 2.75 V	VOCM = 2.75 V
G = 1	100-mV output step

Figure 7-25 Small-Signal Overshoot vs Load Capacitance

VS = 5.5 V	VICM = 2.75 V	VOCM = 2.75 V
Gain = –1	100-mV output step

Figure 7-27 Small-Signal Overshoot vs Load Capacitance

Figure 7-29 No Phase Reversal

VS = 1.8 V			VICM = 0.9 V	VOCM = 0.9 V
CL = 30 pF			Gain = 1	VIN = 100 mVpp

Figure 7-31 Small-Signal Step Response

VS = 5.5 V	VICM = 2.75 V	VOCM = 2.75 V
CL = 0	Gain = 1	5-V step

Figure 7-33 Large Signal Settling Time (Positive)

Figure 7-35 Short-Circuit Current vs Temperature

Figure 7-37 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency

Figure 7-2 Offset Voltage Drift Distribution

Figure 7-4 Offset Voltage vs Common-Mode Voltage

Figure 7-6 Offset Voltage vs Power Supply

Figure 7-8 I_B and I_OS vs Temperature

Figure 7-10 Closed-Loop Gain vs Frequency

Figure 7-12 PSRR vs Frequency (Referred to Input)

VS = 5.5 V

TA = –40°C to 125°C

VCM = 0 V to 4.3 V

Figure 7-14 CMRR vs Temperature

Figure 7-16 Input Voltage Noise Spectral Density vs Frequency

VS = 5.5 V		VICM = 2.5 V	RL = 10 kΩ
Gain = 1		BW = 80 kHz	VOUT = 0.5 Vrms

Figure 7-18 THD + N vs Frequency

Figure 7-20 Quiescent Current vs Supply Voltage

RL = 2 kΩ

Figure 7-22 Open-Loop Gain vs Temperature

AVDD = 5.5 V

VICM = VOCM = 2.75 V

Figure 7-24 Open-Loop Output Impedance vs Frequency

VS = 1.8 V	VICM = 0.9 V	VOCM = 0.9 V
G = 1	100-mV output step

Figure 7-26 Small-Signal Overshoot vs Load Capacitance

VS = 1.8 V	VICM = 0.9 V	VOCM = 0.9 V
Gain = –1	100-mV output step

Figure 7-28 Small-Signal Overshoot vs Load Capacitance

Figure 7-30 Overload Recovery

VS = 5.5 V	VOCM = 2.75 V	CL = 10 pF
VICM = 2.75 V	Gain = 1	2-V step

Figure 7-32 Large Signal Step Response

VS = 5.5 V	VICM = 2.75 V	VOCM = 2.75 V
CL = 0	Gain = 1	5-V step

Figure 7-34 Large Signal Settling Time (Negative)

VICM = VS / 2	VOCM = VS / 2	CL = 10 pF
Gain = 1

Figure 7-36 Maximum Output Voltage vs Frequency

VICM = VOCM = VS / 2

Figure 7-38 Phase Margin vs Capacitive Load