ZHCSMQ4F November   2020  – February 2022 OPA2387 , OPA387 , OPA4387

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA387
    5. 6.5 Thermal Information: OPA2387
    6.     Thermal Information: OPA4387
    7. 6.6 Electrical Characteristics
    8. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Bias Current
      2. 7.3.2 EMI Susceptibility and Input Filtering
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Zero-Drift Clocking
    2. 8.2 Typical Applications
      1. 8.2.1 Bidirectional Current Sensing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Load Cell Measurement
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 PSpice® for TI
        2. 11.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Typical Characteristics

at TA = 25°C, VS = ±2.75 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 50 pF (unless otherwise noted)

GUID-20201027-CA0I-5KDQ-3KMS-L81L73RFXB8P-low.gif
VS = 5.5 V, TA = 25°C
Figure 6-1 Offset Voltage Distribution
GUID-20201027-CA0I-RZTB-J8MS-HF10LFJXL3H8-low.gif
VS = 5.5 V, TA = 125°C
Figure 6-3 Offset Voltage Distribution
GUID-20201027-CA0I-645V-N8XH-2CDTWBK6FLKS-low.gif
 
Figure 6-5 Offset Voltage vs Temperature
GUID-20201027-CA0I-8ZD9-8MDH-PSST3ZFHTDT3-low.gif
 
Figure 6-7 Offset Voltage vs Supply Voltage
GUID-20201203-CA0I-3D0P-V1KZ-2WKB1KX5QNKF-low.gif
 
Figure 6-9 Open-Loop Gain vs Temperature
 
Figure 6-11 Input Bias Current vs Common-Mode Voltage
 
Figure 6-13 PSRR and CMRR vs Frequency
GUID-20201027-CA0I-JVK5-LV1D-PTJDPGQMLHCD-low.gif
 
Figure 6-15 Input Voltage Noise Spectral Density vs Frequency
GUID-20201203-CA0I-T0M1-RJCH-KL22Q60RW0X7-low.gif
VS = 5.5 V, VOUT = 3 VRMS, BW = 80 kHz
 
Figure 6-17 THD+N Ratio vs Frequency
GUID-20201027-CA0I-214T-V8LR-9RRFDJLZZBXP-low.gif
 
Figure 6-19 Quiescent Current vs Supply Voltage
GUID-20201203-CA0I-ZVGW-KPJQ-DGH4JBK1XH1J-low.gif
 
Figure 6-21 Open-Loop Output Impedance vs Frequency
GUID-20201203-CA0I-MH0H-FNM5-RZTQQP7DGVKT-low.gif
G = +1, 10 mV step
Figure 6-23 Small-Signal Overshoot vs Capacitive Load
GUID-20201203-CA0I-FML7-3L1K-SNGDFFQPZLRB-low.gif
 
Figure 6-25 No Phase Reversal
GUID-20201203-CA0I-QZ7B-NCLD-6XQDBXZMBCWC-low.gif
G = +1
Figure 6-27 Small-Signal Step Response
GUID-20201203-CA0I-62HR-RQSG-RTKL6SRBLRB4-low.gif
0.01% settling = ±100 µV
Figure 6-29 Settling Time
GUID-20201027-CA0I-JXSV-9ZXB-NKXMZHW5BWR1-low.gif
VS = 5.5 V, TA = –40°C
Figure 6-2 Offset Voltage Distribution
GUID-20201027-CA0I-5CK4-CZBG-KCCBFTW1ZMNF-low.gif
 VS = 5.5 V
Figure 6-4 Offset Voltage Drift Distribution
GUID-20201027-CA0I-SBGJ-6F4L-PCPL3MGSTXDL-low.gif
 
Figure 6-6 Offset Voltage vs Common-Mode Voltage
GUID-20201027-CA0I-1TBK-HND0-WWM4RPZSB5JM-low.gif
 
Figure 6-8 Open-Loop Gain and Phase vs Frequency
GUID-20201027-CA0I-CWKG-VPJW-LTHFT8RHLPHL-low.gif
 
Figure 6-10 Closed-Loop Gain vs Frequency
GUID-20201203-CA0I-ZNZF-TQJ0-S3GNRBWTRHHX-low.gif
 
Figure 6-12 CMRR vs Temperature
GUID-20201203-CA0I-6TQK-JX4L-K0QQ3GDMN4X1-low.gif
 
Figure 6-14 0.1-Hz to 10-Hz Noise
GUID-20201203-CA0I-DQQL-GGWR-CHPN93JTJNJ7-low.gif
 
Figure 6-16 Channel-to-Channel Crosstalk
GUID-20201203-CA0I-LKCR-P8V0-JFHCXPNSRH9Z-low.gif
VS = 5.5 V, f = 1 kHz, BW = 80 kHz
 
Figure 6-18 THD+N vs Output Amplitude
GUID-20201027-CA0I-LJTP-NF5B-MVKVW20TWL8W-low.gif
 
Figure 6-20 Quiescent Current vs Temperature
GUID-20201203-CA0I-1VJJ-SWK9-Q1SFZMRHJSD8-low.gif
G = –1, 10 mV step
Figure 6-22 Small-Signal Overshoot vs Capacitive Load
G = +1
Figure 6-24 Phase Margin vs Capacitive Load
GUID-20201203-CA0I-VDXH-GZHB-RNXKF3FGP5P5-low.gif
G = –1
Figure 6-26 Overload Recovery
GUID-20201027-CA0I-00C7-HGTC-XNKHQH1DMNGJ-low.gif
4-V step
Figure 6-28 Large-Signal Step Response