Achieving optimum performance with a high-frequency amplifier, such as the OPA3S2859-EP, requires careful attention to board layout parasitics and external component types. Recommendations that optimize performance include the following:

• Reduce capacitive coupling between feedback traces. Trace-to-trace capacitance between the three feedback connection traces can cause the traces to couple together at high frequency and effect the gain of the device. Particularly for high gain feedback configurations, capacitive coupling to feedback paths with lower gain can significantly reduce the bandwidth if not properly isolated. For example, in a circuit configuration with 100k, 10k, and 1k feedback elements, the 100k gain path can see over 66% reduction in bandwidth when using an non-optimized feedback layout. To properly isolate the feedback traces it is important to space the traces out and pour ground plane between the traces to isolate their capcitance; additional trace length, however, does add further inductance and capacitance to the traces which can also effect performance. Therefore, it is important to balance the feedback area and trace length to best minimize the major parasitic effect. A good starting point is to use a design similar to the evaluation module with a feedback area of approximately 6 mm × 6 mm. This can then be adjusted depending on circuit limitations and needs.
• Minimize parasitic capacitance from the signal I/O pins to ac ground. Parasitic capacitance on the output pins can cause instability where as parasitic capacitance on the input pin reduces the amplifier bandwidth. To reduce unwanted capacitance, cut out the power and ground traces under the signal input pins, output pins, and exterior feedback trace when possible. A small value isolation resistor between the DUT output and feedback network can also help reduce the parasitic loading caused by the feedback trace on the output. Otherwise, ground and power planes must be unbroken elsewhere on the board.
• Minimize the distance from the power-supply pins to the high-frequency bypass capacitors. Use high-quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage ratings at least three times greater than the amplifiers maximum power supplies. Place the smallest value capacitors on the same side as the DUT. If space constraints force the larger value bypass capacitors to be placed on the opposite side of the PCB, use multiple vias on the supply and ground side of the capacitors. This configuration makes sure that there is a low-impedance path to the amplifiers power-supply pins across the amplifiers gain bandwidth specification. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors that are effective at lower frequency must be used on the supply pins. Place these decoupling capacitors further from the device. Share the decoupling capacitors among several devices in the same area of the printed circuit board (PCB).