5 Pin Configuration and Functions

Figure 5-1 RTW Package
24-Pin WQFN With Exposed Thermal Pad
Top View

Table 5-1 Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
COM_A	23	I	Photodiode input – Channel A
COM_B	8	I	Photodiode input – Channel B
FB_A0	20	I	Feedback connection to Channel A – TIA Gain Resistor (Low gain, optimized for gain in < 10 kΩ range)
FB_A1	21	I	Feedback connection to Channel A – TIA Gain Resistor (Mid gain, optimized for gain in 10 kΩ – 100 kΩ range)
FB_A2	22	I	Feedback connection to Channel A – TIA Gain Resistor (High gain, optimized for gain in > 100 kΩ range)
FB_B0	11	I	Feedback connection to Channel B – TIA Gain Resistor (Low gain, optimized for gain in < 10 kΩ range)
FB_B1	10	I	Feedback connection to Channel B – TIA Gain Resistor (Mid gain, optimized for gain in 10 kΩ – 100 kΩ range)
FB_B2	9	I	Feedback connection to Channel B – TIA Gain Resistor (High gain, optimized for gain in > 100 kΩ range)
INA-	24	I	Negative (inverting) input for amplifier A
INA+	1	I	Positive (noninverting) input for amplifier A
INB-	7	I	Negative (inverting) input for amplifier B
INB+	6	I	Positive (noninverting) input for amplifier B
LTCH_A	3	I	Latch control input for Channel A. LTCH_A = logic high (default) = transparent mode, gain setting changes based on SEL0 and SEL1 pins are reflected at the output. LTCH_A = logic low = latch mode = changing SEL0 and SEL1 pins does not affect the gain configuration of amplifier.
LTCH_B	4	I	Latch control input for Channel B. LTCH_B = logic high (default) = transparent mode, gain setting changes based on SEL0 and SEL1 pins are reflected at the output. LTCH_B = logic low = latch mode = changing SEL0 and SEL1 pins does not affect the gain configuration of amplifier.
PD	15	I	Power down pin. PD = logic high (default) = normal operation, PD = logic low = power down mode.
SEL0	5	I	TIA gain selection. SEL0 = logic high (default). See Table 5-2 for details.
SEL1	2	I	TIA gain selection. SEL1 = logic high (default). See Table 5-2 for details.
VOUT_A	19	O	Output of amplifier A
VOUT_B	12	O	Output of amplifier B
VS-	13, 18	I	Negative (lowest) power supply
VS+	14, 16, 17	I	Positive (highest) power supply
Thermal pad		—	Connect the thermal pad to the most negative power supply (pin 13 and 18) of the device under test (DUT).

Table 5-2 Select Pin Decoder

SEL1	SEL0	Gain
LOW	HIGH	Low Gain, optimized for gain in < 10 kΩ range
LOW	LOW	Mid Gain, optimized for gain in 10 kΩ – 100 kΩ range
HIGH	LOW	High Gain, optimized for gain in > 100 kΩ range
HIGH (Default)	HIGH (Default)	External Gain. All internal switches open