米6体育平台手机版

ZHCSQB4A May 2022 – August 2022 OPA3S2859

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6.6 Switching Characteristics

V_S+ = 5 V, V_S- = 0 V, input common-mode biased at midsupply, R_F0 = 1 kΩ, R_F1 = 10 kΩ, R_F2 = 100 kΩ, R_L = 200 Ω, output load is referenced to midsupply, and T_A ≈ +25°C (unless otherwise noted), see figure 7-1 for schematic configuration. ⁽¹⁾ ⁽²⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
GAIN SWITCHES
	Switch transition-time ⁽⁵⁾	SW₀ OFF to SW₁ ON		160		ns
		SW₀ OFF to SW₂ ON		230
		SW₁ OFF to SW₀ ON		80
		SW₁ OFF to SW₂ ON		230
		SW₂ OFF to SW₀ ON		80
		SW₂ OFF to SW₁ ON		110
C_COM0	COM capacitance ⁽³⁾ ⁽⁶⁾	SW_COM0 ON; SW_COM1 and SW_COM2 OFF		1.3		pF
C_COM1		SW_COM1 ON; SW_COM0 and SW_COM2 OFF		1.2
C_COM2		SW_COM2 ON; SW_COM0 and SW_COM1 OFF		1.2
C_{COM_OPEN}		SW_COM0 _,SW_COM1 and SW_COM2 OFF		1.2
C_FB0	FB capacitance ⁽⁵⁾ ⁽⁷⁾	SW₀ON		1.9
C_FB1		SW₁ON		1.6
C_FB2		SW₂ON		1.5
C_{FB0_OPEN}		SW₀OFF		1.4
C_{FB1_OPEN}		SW₁OFF		1.2
C_{FB2_OPEN}		SW₂OFF		1.1
R_{ON_COM0}	On resistance ⁽⁸⁾ ⁽⁹⁾			80		Ω
R_{ON_FB0}				38
R_{ON_COM1}				125
R_{ON_FB1}				37
R_{ON_COM2}				375
R_{ON_FB2}				35
	On resistance channel-to-channel matching ⁽³⁾ ⁽⁴⁾	SW_COM0 for Channel A and B		0.15		Ω
		SW_FB0 for Channel A and B		0.4
		SW_COM1 for Channel A and B		0.45
		SW_FB1 for Channel A and B		0.07
		SW_COM2 for Channel A and B		3
		SW_FB2 for Channel A and B		0.12
LOGIC PIN FUNCTION (LATCH, SEL)
	Logic low threshold	Logic low below the threshold voltage	V_S+ - 1.5	V_S+ - 1.3		V
	Logic high threshold	Logic high above the threshold voltage		V_S+ - 1.2	V_S+ - 0.8	V
	Bias current	V_PIN = V_S- or V_S+		6		µA
	Bias current	V_PIN at switching threshold		160		µA
	Setup time		100			ns
	Hold time		100			ns

(1) All the specifications apply for both Channels A and B, unless otherwise noted.

(2) When switching from one gain condition to another, the new gain switches are closed before opening the previous gain switches (make-before-break).

(3) SW_COM0, SW_COM1, SW_COM2 refer to switch on the common-mode side (COM) for the different gain options.

(4) SW_FB0, SW_FB1, SW_FB2 refer to switch on the feedback side (FB) for the different gain options.

(5) SW₀, SW₁, SW₂ refers to the two switches needed for a given gain condition. For example, SW0 refers to SW_COM0 and SW_FB0.

(6) C_COM0, C_COM1, C_COM2is the capacitance at the COM pin for different gain options. It is equal to ON capacitance of closed switch + OFF capacitance of open switches.

(7) C_FB0, C_FB1, C_FB2 is the capacitance at the FB_X pin. It is equal to ON capacitance of the gain option selected (SW_COM0 + SW_FB0 capacitance).

(8) R_{ON_COM0}, R_{ON_COM1}, R_{ON_COM2}, refer to ON resistance for the COM side switch.

(9) R_{ON_FB0}, R_{ON_FB1}, R_{ON_FB2}, refer to ON resistance for the FB side switch.

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6.6 Switching Characteristics