ZHCSLZ5D October 2020 – December 2023 OPA3S328
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Parameter Measurement Information
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
- RGR|20
订购信息
4 Pin Configuration and Functions
Figure 4-1 RGR Package, 20-Pin VQFN
(Top View)
Figure 4-2 YBJ Package, 24-Pin DSBGA
(Top View)Table 4-1 Pin Functions
| PIN | TYPE | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | |||
| RGR (VQFN) | YBJ (DSBGA) | |||
| DNC | — | B4, C4, D4 | — | Do not connect |
| GND | 3 | C5 | Ground | Digital ground pin |
| –INA | 18 | A1 | Input | Negative (inverting) input for amplifier A |
| –INB | 8 | E1 | Input | Negative (inverting) input for amplifier B |
| +INA | 17 | A3 | Input | Positive (noninverting) input for amplifier A |
| +INB | 9 | E3 | Input | Positive (noninverting) input for amplifier B |
| INSA | 16 | B2 | Input/Output | Switch A1, A2, A3 input |
| INSB | 10 | D2 | Input/Output | Switch B1, B2, B3 input |
| OUTA | 19 | A2 | Output | Output of amplifier A |
| OUTB | 7 | E2 | Output | Output of amplifier B |
| OUTSA1 | 14 | C1 | Input/Output | Switch A1 output |
| OUTSA2 | 15 | B1 | Input/Output | Switch A2 output |
| OUTSA3 | — | B3 | Input/Output | Switch A3 output |
| OUTSB1 | 13 | C2 | Input/Output | Switch B1 output |
| OUTSB2 | 12 | D1 | Input/Output | Switch B2 output |
| OUTSB3 | 11 | D3 | Input/Output | Switch B3 output |
| SELA0 | 2 | B5 | Input | Input select for switch matrix A |
| SELA1 | 1 | A4 | Input | Input select for switch matrix A |
| SELB0 | 4 | D5 | Input | Input select for switch matrix B |
| SELB1 | 5 | E4 | Input | Input select for switch matrix B |
| V– | 6 | E5 | Power | Negative (lowest) power supply |
| V+ | 20 | A5 | Power | Positive (highest) power supply |
| Thermal Pad | Thermal Pad | — | — | Exposed thermal pad. Connect to V– |
Table 4-2 Select Pin Decoder
| SELA1 | SELA0 | SELB1 | SELB0 | SHUTDOWN STATUS | SWITCH CONFIGURATION | |||||
|---|---|---|---|---|---|---|---|---|---|---|
| SWITCH A1 STATUS | SWITCH A2 STATUS | SWITCH A3(1) STATUS | SWITCH B1 STATUS | SWITCH B2 STATUS | SWITCH B3 STATUS | |||||
| LOW | LOW | — | — | Amplifier A enabled | CLOSED | OPEN | OPEN | — | — | — |
| LOW | HIGH | — | — | Amplifier A enabled | OPEN | CLOSED | OPEN | — | — | — |
| HIGH | LOW | — | — | Amplifier A enabled | OPEN | OPEN | CLOSED | — | — | — |
| HIGH | HIGH | — | — | In special mode, the SELB0 and SELB1 decoding scheme shown here is ignored, and instead, Table 4-3 applies. | — | — | — | |||
| — | — | LOW | LOW | Amplifier B enabled | — | — | — | CLOSED | OPEN | OPEN |
| — | — | LOW | HIGH | Amplifier B enabled | — | — | — | OPEN | CLOSED | OPEN |
| — | — | HIGH | LOW | Amplifier B enabled | — | — | — | OPEN | OPEN | CLOSED |
| — | — | HIGH | HIGH | Amplifier B enabled | — | — | — | OPEN | OPEN | OPEN |
(1) Switch A3 is available in the YBJ
(DSBGA-24) package option only.
Table 4-3 Select Pin Decoder in Special Mode:
SELA0 = SELA1 = HIGH
| SELA1 | SELA0 | SELB1 | SELB0 | SHUTDOWN STATUS | SWITCH CONFIGURATION | |||||
|---|---|---|---|---|---|---|---|---|---|---|
| SWITCH A1 STATUS | SWITCH A2 STATUS | SWITCH A3(1) STATUS | SWITCH B1 STATUS | SWITCH B2 STATUS | SWITCH B3 STATUS | |||||
| HIGH | HIGH | LOW | LOW | Amplifier A in power down and amplifier B enabled | OPEN | OPEN | OPEN | OPEN | OPEN | OPEN |
| HIGH | HIGH | LOW | HIGH | Amplifier A enabled and amplifier B in power down | OPEN | OPEN | OPEN | OPEN | OPEN | OPEN |
| HIGH | HIGH | HIGH | LOW | Both Amplifier A and amplifier B enabled | OPEN | OPEN | OPEN | OPEN | OPEN | OPEN |
| HIGH | HIGH | HIGH | HIGH | Both Amplifier A and amplifier B in power down | OPEN | OPEN | OPEN | OPEN | OPEN | OPEN |
(1) Switch A3 is available in the YBJ
(DSBGA-24) package option only.