For best operational performance of the device, use good PCB layout practices, including:
- Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
- Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications.
- Separate grounding for analog and digital
portions of circuitry is one of the simplest and most-effective methods
of noise suppression. One or more layers on multilayer PCBs are usually
devoted to ground planes. A ground plane helps distribute heat and
reduces EMI noise pickup. Make sure to physically separate digital and
analog grounds paying attention to the flow of the ground current. For
more detailed information, see Circuit Board Layout
Techniques.
- To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
- Place the external components as close to the device as possible. As illustrated in Figure 8-3, keeping RF and RG close to the inverting input minimizes parasitic capacitance.
- Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
- Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.
- For best performance, TI recommends cleaning the PCB following board assembly.
- Any precision integrated circuit can experience
performance shifts due to moisture ingress into
the plastic package. Following any aqueous PCB
cleaning process, TI recommends baking the PCB
assembly to remove moisture introduced into the
device packaging during the cleaning process. A
low temperature, post cleaning bake at 85°C for 30
minutes is sufficient for most circumstances.
In addition, follow these steps for the DRG package:
- Solder the thermal pad to a V− plane to conduct heat away from the package. Thermal
vias underneath the thermal pad are recommended, but not required. The recommended
pattern is shown in the mechanical drawing appended to the end of this document. If
using thermal vias connect to the V− plane.
- When connecting these vias to the plane, do not
use the typical web or spoke via connection
methodology. Web connections have a high thermal
resistance connection that is useful for slowing
the heat transfer during soldering operations,
making the soldering of vias that have plane
connections easier. In this application, however,
low thermal resistance is desired for the most
efficient heat transfer. Therefore, the vias under
the package must make the connections to the
internal plane with a complete connection around
the entire circumference of the plated-through
hole.
- The top-side solder mask must leave the pins of
the package and the thermal pad area exposed. The
bottom-side solder mask must cover the vias of the
thermal pad area. This masking prevents solder
from being pulled away from the thermal pad area
during the reflow process.
- Apply solder paste to the exposed thermal pad
area and all of the device pins.
- With these preparatory steps in place, simply
place the device in position, and run through the
solder reflow operation as with any standard
surface-mount component