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ZHCSEI8C January 2016 – March 2018 OPA197 , OPA2197 , OPA4197

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

PW|14
- MPDS360A
D|14
- MPDS177H

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.9 Typical Characteristics

Table 1. Table of Graphs

DESCRIPTION	FIGURE
Offset Voltage Production Distribution	Figure 1, Figure 2, Figure 3
Offset Voltage Drift Distribution	Figure 4
Offset Voltage vs Temperature	Figure 5
Offset Voltage vs Common-Mode Voltage	Figure 6, Figure 7, Figure 8
Offset Voltage vs Power Supply	Figure 9
Open-Loop Gain and Phase vs Frequency	Figure 10
Closed-Loop Gain and Phase vs Frequency	Figure 11
Input Bias Current vs Common-Mode Voltage	Figure 12
Input Bias Current vs Temperature	Figure 13
Output Voltage Swing vs Output Current (maximum supply)	Figure 14, Figure 15
CMRR and PSRR vs Frequency	Figure 16
CMRR vs Temperature	Figure 17
PSRR vs Temperature	Figure 18
0.1-Hz to 10-Hz Noise	Figure 19
Input Voltage Noise Spectral Density vs Frequency	Figure 20
THD+N Ratio vs Frequency	Figure 21
THD+N vs Output Amplitude	Figure 22
Quiescent Current vs Supply Voltage	Figure 23
Quiescent Current vs Temperature	Figure 24
Open Loop Gain vs Temperature	Figure 25
Open Loop Output Impedance vs Frequency	Figure 26
Small Signal Overshoot vs Capacitive Load (100-mV output step)	Figure 27, Figure 28
No Phase Reversal	Figure 29
Positive Overload Recovery	Figure 30
Negative Overload Recovery	Figure 31
Small-Signal Step Response (100 mV)	Figure 32, Figure 33
Large-Signal Step Response	Figure 34
Settling Time	Figure 35, Figure 36, ,
Short-Circuit Current vs Temperature	Figure 37
Maximum Output Voltage vs Frequency	Figure 38
Propagation Delay Rising Edge	Figure 39
Propagation Delay Falling Edge	Figure 40

at T_A = 25°C, V_S = ±18 V, V_CM = V_S / 2, R_LOAD = 10 kΩ connected to V_S / 2, and C_L = 100 pF (unless otherwise noted)


4770 production units

Figure 1. Offset Voltage Production Distribution at 25°C

Figure 3. Offset Voltage Production Distribution at –40°C


	9 typical units

Figure 5. Offset Voltage vs Temperature


	6 typical units

Figure 7. Offset Voltage vs Common-Mode Voltage


	6 typical units

Figure 9. Offset Voltage vs Power Supply

Figure 11. Closed-Loop Gain and Phase vs Frequency

Figure 13. Input Bias Current vs Temperature

Figure 15. Output Voltage Swing from Positive Power Supply vs Output Current (Maximum Supply)

Figure 17. CMRR vs Temperature

Peak-to-peak noise = V_RMS × 6.6 = 1.30 V_PP

Figure 19. 0.1-Hz to 10-Hz Noise


V_OUT = 3.5 V_RMS, BW = 80 kHz

Figure 21. THD+N Ratio vs Frequency

Figure 23. Quiescent Current vs Supply Voltage

Figure 25. Open-Loop Gain vs Temperature


	G = –1 V/V

Figure 27. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)


V_S = ±18 V, input = ±18.5 V_PP

Figure 29. No Phase Reversal


	G = –10 V/V

Figure 31. Negative Overload Recovery


G = –1 V/V

Figure 33. Small-Signal Step Response


G = 1, 0.01% settling = ±1 mV, step applied at t = 0

Figure 35. Settling Time (10-V Positive Step)

Figure 37. Short-Circuit Current vs Temperature

Figure 39. Propagation Delay Rising Edge

Figure 2. Offset Voltage Production Distribution at 125°C

Figure 4. Offset Voltage Drift Distribution
from –40°C to +125°C


	6 typical units

Figure 6. Offset Voltage vs Common-Mode Voltage


	6 typical units

Figure 8. Offset Voltage vs Common-Mode Voltage


C_LOAD = 15 pF

Figure 10. Open-Loop Gain and Phase vs Frequency

Figure 12. Input Bias Current vs Common-Mode Voltage

Figure 14. Output Voltage Swing from Negative Power Supply vs Output Current (Maximum Supply)

Figure 16. CMRR and PSRR vs Frequency

Figure 18. PSRR vs Temperature

Figure 20. Input Voltage Noise Spectral Density
vs Frequency


f = 1 kHz, BW = 80 kHz

Figure 22. THD+N vs Output Amplitude

Figure 24. Quiescent Current vs Temperature

Figure 26. Open-Loop Output Impedance vs Frequency


	G = 1 V/V

Figure 28. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)


	G = –10 V/V

Figure 30. Positive Overload Recovery


G = 1 V/V

Figure 32. Small-Signal Step Response


G = 1 V/V

Figure 34. Large-Signal Step Response


G = 1, 0.01% settling = ±500 µV, step applied at t = 0

Figure 36. Settling Time (5-V Positive Step)

Figure 38. Maximum Output Voltage vs Frequency

Figure 40. Propagation Delay Falling Edge