SBOS432G August 2008 – August 2016 OPA2330 , OPA330 , OPA4330
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configurations and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封装选项
请参考 PDF 数据表获取器件具体的封装图。
机械数据 (封装 | 引脚)
- D|14
- RGY|14
- PW|14
散热焊盘机械数据 (封装 | 引脚)
- RGY|14
订购信息
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Voltage | Supply, VS = (V+) – (V–) | 7 | V | |
| Signal input terminals(2) (TBD should terminal be pin?) | (V–) –0.3 | (V+) + 0.3 | V | |
| Current | Signal input terminals(2) | –10 | 10 | mA |
| Output short-circuit(3) | Continuous | |||
| Temperature | Operating range, TA | –40 | 150 | °C |
| Junction, TJ | 150 | °C | ||
| Storage, Tstg | –65 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
| Machine model (MM) | ±400 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| (V+) – (V–) | Supply voltage | ±0.9 (1.8) | ±2.5 (5) | ±2.75 (5.5) | V |
| TA | Specified temperature | –40 | 25 | 125 | °C |
7.4 Thermal Information: OPA330
| THERMAL METRIC(1) | OPA330 | UNIT | ||||
|---|---|---|---|---|---|---|
| D (SOIC) | DBV (SOT-23) | DCK (SC70) | YFF (DSBGA) | |||
| 8 PINS | 5 PINS | 5 PINS | 5 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 140.1 | 220.8 | 298.4 | 130 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 89.8 | 97.5 | 65.4 | 54 | °C/W |
| RθJB | Junction-to-board thermal resistance | 80.6 | 61.7 | 97.1 | 51 | °C/W |
| ψJT | Junction-to-top characterization parameter | 28.7 | 7.6 | 0.8 | 1 | °C/W |
| ψJB | Junction-to-board characterization parameter | 80.1 | 61.1 | 95.5 | 50 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.5 Thermal Information: OPA2330
| THERMAL METRIC(1) | OPA2330 | UNIT | |||
|---|---|---|---|---|---|
| D (SOIC) | DGK (VSSOP) | DRB (SON) | |||
| 8 PINS | 8 PINS | 8 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 124 | 180.3 | 46.7 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 73.7 | 48.1 | 26.3 | °C/W |
| RθJB | Junction-to-board thermal resistance | 64.4 | 100.9 | 22.2 | °C/W |
| ψJT | Junction-to-top characterization parameter | 18 | 2.4 | 1.6 | °C/W |
| ψJB | Junction-to-board characterization parameter | 63.9 | 99.3 | 22.3 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | 10.1 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.6 Thermal Information: OPA4330
| THERMAL METRIC(1) | OPA4330 | UNIT | |||
|---|---|---|---|---|---|
| D (SOIC) | PW (TSSOP) | RGY (VQFN) | |||
| 14 PINS | 14 PINS | 14 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 83.8 | 120.8 | 49.2 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 70.7 | 34.3 | 75.3 | °C/W |
| RθJB | Junction-to-board thermal resistance | 59.5 | 62.8 | 61.9 | °C/W |
| ψJT | Junction-to-top characterization parameter | 11.6 | 1 | 1.2 | °C/W |
| ψJB | Junction-to-board characterization parameter | 37.7 | 56.5 | 19.3 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | 4.6 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.7 Electrical Characteristics
at TA = 25°C, RL = 10 kΩ connected to midsupply, VS = 1.8 V to 5.5 V, and VCM = VOUT = midsupply (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| OFFSET VOLTAGE | ||||||||
| VOS | Input offset voltage | VS = 5 V | 8 | 50 | µV | |||
| dVOS/dT | Input offset voltage versus temperature | At TA = –40°C to +125°C | 0.02 | 0.25 | µV/°C | |||
| PSRR | Input offset voltage versus power supply | At TA = –40°C to +125°C | 1 | 10 | µV/V | |||
| Long-term stability(1) | VS = 1.8 V to 5.5 V | See (1) | ||||||
| Channel separation, dc | 0.1 | µV/V | ||||||
| INPUT BIAS CURRENT | ||||||||
| IB | Input bias current | At 25°C | ±200 | ±500 | pA | |||
| OPA330YFF, OPA4330 | ±70 | ±300 | pA | |||||
| At TA = –40°C to +125°C | ±300 | pA | ||||||
| IOS | Input offset current | At 25°C | ±400 | ±1000 | pA | |||
| OPA330YFF, OPA4330 | ±140 | ±600 | pA | |||||
| NOISE | ||||||||
| en | Input voltage noise density | f = 1 kHz | 55 | nV/√Hz | ||||
| Input voltage noise | f = 0.01 Hz to 1 Hz | 0.3 | µVPP | |||||
| f = 0.1 Hz to 10 Hz | 1.1 | µVPP | ||||||
| in | Input current noise | f = 10 Hz | 100 | fA/√Hz | ||||
| INPUT VOLTAGE RANGE | ||||||||
| VCM | Common-mode voltage range | (V–) – 0.1 | (V+) + 0.1 | V | ||||
| CMRR | Common-mode rejection ratio | At TA = –40°C to +125°C, (V–) – 0.1 V < VCM < (V+) + 0.1 V |
100 | 115 | dB | |||
| At TA = –40°C to +125°C, (V–) – 0.1 V < VCM < (V+) + 0.1 V, VS = 5.5 V |
100 | 115 | dB | |||||
| OPA330YFF, OPA4330 | 100 | 115 | dB | |||||
| INPUT CAPACITANCE | ||||||||
| Differential | 2 | pF | ||||||
| Common-mode | 4 | pF | ||||||
| OPEN-LOOP GAIN | ||||||||
| AOL | Open-loop voltage gain | At TA = –40°C to +125°C, (V–) + 100 mV < VO < (V+) – 100 mV, RL = 10 kΩ |
100 | 115 | dB | |||
| FREQUENCY RESPONSE | ||||||||
| GBW | Gain-bandwidth product | CL = 100 pF | 350 | kHz | ||||
| SR | Slew rate | G = +1 | 0.16 | V/µs | ||||
| OUTPUT | ||||||||
| Voltage output swing from rail | At TA = –40°C to +125°C | 30 | 100 | mV | ||||
| ISC | Short-circuit current | ±5 | mA | |||||
| CL | Capacitive load drive | See Typical Characteristics | ||||||
| Open-loop output impedance | f = 350 kHz, IO = 0 mA | 2 | kΩ | |||||
| POWER SUPPLY | ||||||||
| VS | Specified voltage range | 1.8 | 5.5 | V | ||||
| IQ | Quiescent current per amplifier | At TA = –40°C to +125°C, IO = 0 mA | 21 | 35 | µA | |||
| Turnon time | VS = 5 V | 100 | µs | |||||
(1) 300-hour life test at 150°C demonstrated randomly distributed variation of approximately 1 µV.
7.8 Typical Characteristics
At TA = 25°C, CL = 0 pF, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply, unless otherwise noted.Table 1. Table of Graphs
| DESCRIPTION | FIGURE NO. | |
|---|---|---|
| Offset Voltage Production Distribution | Figure 1 | |
| Open-Loop Gain vs Frequency | Figure 2 | |
| Common-Mode Rejection Ratio vs Frequency | Figure 3 | |
| Power-Supply Rejection Ratio vs Frequency | Figure 4 | |
| Output Voltage Swing vs Output Current | Figure 5 | |
| Input Bias Current vs Common-Mode Voltage | Figure 6 | |
| Input Bias Current vs Temperature | Figure 7 | |
| Quiescent Current vs Temperature | Figure 8 | |
| Large-Signal Step Response | Figure 9 | |
| Small-Signal Step Response | Figure 10 | |
| Positive Overvoltage Recovery | Figure 11 | |
| Negative Overvoltage Recovery | Figure 12 | |
| Settling Time vs Closed-Loop Gain | Figure 13 | |
| Small-Signal Overshoot vs Load Capacitance | Figure 14 | |
| 0.1-Hz to 10-Hz Noise | Figure 15 | |
| Current and Voltage Noise Spectral Density vs Frequency | Figure 16 | |
| Input Bias Current vs Input Differential Voltage | Figure 17 | |
