ZHCSOX1 October   2020 OPA455

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Status Flag Pin
      2. 7.3.2 Thermal Protection
      3. 7.3.3 Current Limit
      4. 7.3.4 Enable and Disable
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 High DAC Gain Stage for Semiconductor Test Equipment
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Improved Howland Current Pump for Bioimpedance Measurements in Multiparameter Patient Monitors
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Thermally-Enhanced PowerPAD™ Package
      2. 10.1.2 PowerPAD™ Integrated Circuit Package Layout Guidelines
      3. 10.1.3 Pin Leakage
      4. 10.1.4 Thermal Protection
      5. 10.1.5 Power Dissipation
      6. 10.1.6 Heat Dissipation
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI™ Simulation Software (Free Download)
        2. 11.1.1.2 TI Precision Designs
        3. 11.1.1.3 WEBENCH® Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

at TA = 25°C, VS = ±75V  RL = 10 kΩ to mid-supply, VCM = VOUT = mid-supply (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage IO = 0 mA ±0.2 ±3.4 mV
dVOS/dT Input offset voltage drift TA = –40°C to +85°C ±4 ±20 µV/°C
PSRR Power supply rejection ratio VS = ±6 V to ±75 V 0.03 0.3 µV/V
VS = ±6 V to ±75 V,
TA = –40°C to +85°C		 0.3 1.5
INPUT BIAS CURRENT
IB Input bias current VS = ±50 V ±30 ±100 pA
TA = –40°C to +85°C ±1.8 nA
IOS Input offset current ±30 ±100 pA
TA = –40°C to +85°C ±1 nA
NOISE
en Input voltage noise density f = 1 kHz 33 nV/√Hz
f = 10 kHz 23
Input voltage noise f = 0.1 Hz to 10 Hz 12 µVPP
in Current noise density f = 1 kHz 40 fA/√Hz
f = 10 kHz 450
INPUT VOLTAGE
VCM Common-mode voltage Linear operation (V–) + 1 (V+) – 3 V
CMRR Common-mode rejection –75 V ≤ VCM ≤ 75 V 120 128 dB
–75 V ≤ VCM ≤ 75 V,
TA = –40°C to +85°C		 120 128
INPUT IMPEDANCE
Differential 1013 || 6 Ω || pF
Common-mode 1013 || 3.5 Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 3 V < VO < (V+) – 3 V 126 135 dB
(V–) + 3 V < VO < (V+) – 3 V,
TA = –40°C to +85°C		 120 134
(V–) + 5 V < VO < (V+) – 5 V,
RL = 5kΩ		 126 135
(V–) + 5 V < VO < (V+) – 5 V,
RL = 5kΩ,
TA = –40°C to +85°C		 120 130
FREQUENCY RESPONSE
GBW Gain-bandwidth product Small-signal 6.5 MHz
SR Slew rate G = ±1 V/V, VO = 80-V step,
RL = 3.27 kΩ		 32 V/µs
Full-power bandwidth 33 kHz
tS Settling time To ±0.01%,
G = ±5 V/V or ±10 V/V,
VO = 120-V step		 5.2 µs
THD+N Total harmonic distortion + noise G = +10 V/V,
f = 1 kHz, VO = 140 VPP 		0.0009 %
G = +10 V/V,
f = 1 kHz, VO = 140 VPP,
RL = 5 kΩ		 0.0012
G = +20 V/V,
f = 1 kHz, VO = 140 VPP 		0.0015
G = +20 V/V,
f = 1 kHz, VO = 140 VPP,
RL = 5 kΩ		 0.0025
OUTPUT
Overload recovery G = –10 V/V 140 ns
VO Output voltage swing RL = 10 kΩ (V–) + 3 (V+) – 1.5 V
RL = 5 kΩ (V–) + 5 (V+) – 3
ISC Short-circuit current VS = ±45 V,
TA = –40°C to +85°C		 ±45 mA
CLOAD Capacitive load drive 200 pF
ZO Open-loop output impedance f = 1 MHz 90 Ω
Output impedance Output disabled 160 kΩ
Output capacitance Output disabled 36 pF
STATUS FLAG PIN (Referenced to E/D Com)
Status Flag delay Enable → Disable,
10-kΩ pullup to 5 V		 3.5 µs
Disable → Enable,
10-kΩ pullup to 5 V		 11
Overcurrent delay,
10-kΩ pullup to 5 V		 1
Overcurrent recovery delay,
10-kΩ pullup to 5 V		 9
Device thermal shutdown Alarm (Status Flag high) 150 °C
Return to normal operation
(Status Flag low)		 130
Status Flag output voltage Normal operation See typical curves V
E/D (ENABLE/DISABLE) PIN
VSD High (output enabled) Pin open or forced high E/D Com + 0.8 E/D Com + 5.5 V
Low (output disabled) Pin forced low E/D Com E/D Com + 0.35
Output disable time 4 µs
Output enable time 2.5 µs
E/D COM PIN
Pin voltage VS ≥ 106 V (V–) (V–) +100 V
VS < 106 V (V–) (V+) – 6
POWER SUPPLY
IQ Quiescent current IO = 0 mA 3.2 3.7 mA
Quiescent current in Shutdown mode IO = 0 mA, VE/D = 0.65 V 1.5 2 mA
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