米6体育平台手机版

ZHCS228A June 2011 – February 2024 OPA564-Q1

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

DWP|20
- MPDS032B

散热焊盘机械数据 (封装 | 引脚)

DWP|20
- PPTD006E

订购信息

6.5 Electrical Characteristics

at T_CASE = +25°C, V_S = ±12V, R_LOAD = 20kΩ to GND, R_SET = 7.5kΩ, and E/S pin enabled (unless otherwise noted)

PARAMETERS		TEST CONDITIONS		MIN	TYP	MAX	UNIT
OFFSET VOLTAGE
V_OS	Input offset voltage	V_CM = 0V			±2	±20	mV
dV_OS/dT	vs temperature	T_A = –40°C to +125°C			±10		μV/°C
PSRR	vs power supply	V_CM = 0V, V_S = ±3.5V to ±13V			10	150	μV/V
INPUT BIAS CURRENT
I_B	Input bias current⁽¹⁾	V_CM = 0V			10	100	pA
	vs temperature	T_A = –40°C to +125°C		See Figure 6-10
I_OS	Input offset current⁽¹⁾				10	100	pA
NOISE
e_n	Input voltage noise density	f = 1kHz			102.8		nV/√ Hz
		f = 10kHz			20		nV/√ Hz
		f = 100kHz			8		nV/√ Hz
I_n	Input current noise	f = 1kHz			4		fA/√ Hz
INPUT VOLTAGE RANGE
V_CM	Common-mode voltage	Linear operation		(V–)		(V+) – 3	V
CMRR	Common-mode rejection ratio	V_CM = (V–) to (V+) – 3V		70	80		dB
CMRR	Common-mode rejection ratio	V_CM = (V–) to (V+) – 3V, T_A = –40°C to +125°C		See Figure 6-9
INPUT IMPEDANCE
	Input impedance	Differential			10¹² \|\| 16		Ω \|\| pF
	Input impedance	Common-mode			10¹² \|\| 9		Ω \|\| pF
OPEN-LOOP GAIN
A_OL	Open-loop voltage gain	V_OUT = 20V_PP, R_LOAD = 1kΩ		80	108		dB
A_OL	Open-loop voltage gain	V_OUT = 20V_PP, R_LOAD = 10Ω			93		dB
FREQUENCY RESPONSE
GBW	Gain-bandwidth product⁽¹⁾	R_LOAD = 5Ω			17		MHz
SR	Slew rate	G = 1, 10V step			40		V/μs
	Full power bandwidth	G = +2, V_OUT = 10V_PP			1.3		MHz
	Settling time	G = +1, 10V step, C_LOAD = 100pF	±0.1%		0.6		μs
	Settling time	G = +1, 10V step, C_LOAD = 100pF	±0.01%		0.8		μs
THD+N	Total harmonic distortion + noise	f = 1kHz, R_LOAD = 5Ω, G = +1, V_OUT = 5V_P			0.003		%
OUTPUT
V_OUT	Voltage output	Positive	I_OUT = 0.5A	(V+) – 1	(V+) – 0.4		V
		Positive	I_OUT = 1.5A	(V+) – 2	(V+) – 1.5		V
		Negative	I_OUT = –0.5A	(V–) + 1	(V–) + 0.3		V
		Negative	I_OUT = –1.5A	(V–) + 2	(V–) + 1.1		V
I_OUT	Maximum continuous current, dc				1.5⁽²⁾		A
R_O	Output impedance, closed loop	f = 100kHz			10		Ω
Z_O	Output impedance, open loop	G = +2, f = 100kHz		See Figure 6-24
	Output current limit range⁽³⁾				±0.4 to ±1.9		A
I_LIM	Current limit equation			$I_{L I M} ≅ 20 k \times [\frac{1.2 V}{5 k Ω + R_{S E T}}]$ ⁽⁴⁾⁽⁵⁾			A
I_LIM	Current limit equation	Solved for R_SET (current limit)		R_SET ≅ (24kΩ / I_LIM) – 5kΩ			Ω
	Current limit accuracy	I_LIM = 1.5A			10		%
	Current limit overshoot⁽¹⁾⁽⁶⁾	V_IN = 5V pulse (200ns t_r), G = +2			50		%
	Output impedance⁽⁷⁾	Output shutdown		6 \|\| 120			GΩ \|\| pF
C_LOAD	Capacitive load drive			See Figure 6-6
DIGITAL CONTROL
	V_{E/ S} high (output enabled)	V_DIG = 3.3V to 5.5V referenced to V–	E/S pin open or forced high	(V–) + 2		(V–) + V_DIG	V
	V_{E/ S} Low (output shut down)		E/S pin forced low	(V–)		(V–) + 0.8	V
	I_E/S high (output enabled)		E/S pin indicates high		10		μA
	I_E/S low (output shut down)		E/S pin indicates low		1		μA
	Output shutdown time				1		μs
	Output enable time				3		μs
	Current limit flag output	Normal operation, sinking 10μA			V–	(V–) + 0.8	V
	Current limit flag output	Current-limited operation, sourcing 20μA		(V–) + 2	V_DIG		V
THERMAL SHUTDOWN
	Normal operation	Sinking 200μA			V–	(V–) + 0.8	V
	Thermal shutdown⁽⁸⁾	Sourcing 200μA		(V–) + 2	V_DIG		V
	Junction temperature at shutdown⁽⁹⁾				140 to 157		°C
	Hysteresis⁽⁹⁾				15 to 19		°C
T_SENSE
η	Diode ideality factor				1.033
POWER SUPPLY⁽¹⁰⁾
I_Q	Quiescent current⁽⁴⁾	I_OUT = 0A			39	50	mA
I_Q	Quiescent current⁽⁴⁾	I_OUT = 0A, T_A = –40°C to 125°C				50	mA
I_QSD	Quiescent current in shutdown mode					5	mA
I_DIG	Digital quiescent current	V_DIG = 5V			43	100	μA

(1) See Section 6.6.

(2) Under safe operating conditions; see also Section 8.1.4.

(3) Minimum current limit is 0.4A; see also Section 7.3.1.

(4) Quiescent current increases when the current limit is increased (see also Figure 6-33).

(5) R_SET (current limit) ranges from 55kΩ (I_OUT = 400mA) to 10kΩ (I_OUT = 1.6A typical); see also Section 7.3.1.

(6) Transient load transition time must be ≥ 200ns.

(7) See also Section 7.3.2.

(8) When sourcing, the V_DIG supply must be able to supply the current.

(9) Characterized, but not production tested.

(10) Power-supply sequencing requirements must be observed. See Section 8.3 for more information.