Figure 8-12 shows two examples of generating the signal for V_DIG. Figure 8-12(a) uses an 1N4732A zener to bias the V_DIG to precisely 4.7V greater than V–. Figure 8-12(b) uses a high-voltage subregulator to derive the V_DIG voltage. Ensure that any decoupling capacitance present on the VDIG pin does not cause a timing condition that violates the power-supply sequencing outlined in Section 8.3.

Figure 8-12 Circuits to Generate V_DIG