米6体育平台手机版

ZHCSDL0A April 2015 – October 2015 OPA2625 , OPA625

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

DBV|6
- MPDS026Q

散热焊盘机械数据 (封装 | 引脚)

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage, V_S	(V+) – (V–)		6	V
Input voltage⁽²⁾	+IN	(V–) – 0.3	(V+) + 0.3	V
	–IN	(V–) – 0.3	(V+) + 0.3
	MODE	(V–) – 0.3	(V+) + 0.3
Output voltage	OUT	(V–)	(V+)	V
Sink current	+IN		10	mA
	–IN		10
	MODE		10
	OUT		150
Source current	+IN		10	mA
	–IN		10
	MODE		10
	OUT⁽²⁾		150
Temperature	Operating junction	–40	150	°C
Temperature	Storage, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) For input voltages beyond the power-supply rails, voltage or current must be limited.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±3000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_S	Supply input voltage, (V+) – (V–)		2.7	5.5	V
V_I	Input voltage	+IN	(V–)	(V+) – 1.15	V
		–IN	(V–)	(V+) – 1.15
		MODE	(V–)	(V+)
V_O	Output voltage		(V–)	(V+)	V
I_O	Output current		–120	120	mA
T_A	Operating free-air temperature		–40	125	°C
T_J	Operating junction temperature		–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		OPA625	OPA2625	UNIT
		DBV (SOT)	DGS (VSSOP)
		6 PINS	10 PINS
R_θJA	Junction-to-ambient thermal resistance	184.9	171.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	123.6	68.4	°C/W
R_θJB	Junction-to-board thermal resistance	30.7	91.9	°C/W
ψ_JT	Junction-to-top characterization parameter	22.1	9.4	°C/W
ψ_JB	Junction-to-board characterization parameter	30.2	90.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics High-Drive Mode

at T_A = 25°C, V+ = 5 V, V– = 0 V, MODE pin connected to V– pin, V_COM = V_O = 2.5 V, gain (G) = 1, R_F = 1 kΩ, C_F = 2.7 pF, C_LOAD = 20 pF, and R_LOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
AC PERFORMANCE
	Unity gain frequency	V_O = 10 mV_PP			80		MHz
φ_m	Phase margin				50		Degrees
GBW	Gain-bandwidth product	G = 100, V_O = 10 mV_PP			120		MHz
SR	Slew rate	V_O = 1-V step, G = 1			45		V/µs
SR	Slew rate	V_O = 4-V step, G = 2			115		V/µs
t_settle	Settling time	V_O = 4-V step, G = 2	Settling time to 0.1% (10-bit accuracy)		80		ns
			to 0.005% (14-bit accuracy)		110
			to 0.00153% (16-bit accuracy)		280
	Overshoot	V_O = 4-V step, G = 2			2.5%
	Undershoot	V_O = 4-V step, G = 2			3%
HD2	Second-order harmonic Distortion	V_O = 2 V_PP, G = 2	f = 10 kHz		144		dBc
			f = 100 kHz		122
			f = 1 MHz		80
HD3	Third-order harmonic Distortion	V_O = 2 V_PP, G = 2	f = 10 kHz		155		dBc
			f = 100 kHz		140
			f = 1 MHz		80
	Second-order intermodulation distortion	V_O = 2 V_PP, f = 1 MHz, 200-kHz tone spacing			90		dBc
	Third-order intermodulation distortion	V_O = 2 V_PP, f = 1 MHz, 200-kHz tone spacing			100		dBc
V_N	Input noise voltage	f = 0.1 Hz to 10 Hz, peak-to-peak			0.8		µV_PP
V_N	Input noise voltage	f = 0.1 Hz to 10 Hz, rms			120		nV_RMS
V_n	Input voltage noise density	f = 1 kHz			3.2		nV/√Hz
V_n	Input voltage noise density	f = 10 kHz			2.5		nV/√Hz
I_n	Input current noise density	f = 1 kHz			4.1		pA/√Hz
I_n	Input current noise density	f = 10 kHz			2.8		pA/√Hz
t_OR	Overload recovery time	G = 5			50		ns
Z_o	Open-loop output impedance	f = 1 MHz			1		Ω
	Crosstalk	DC			150		dB
	Crosstalk	f = 1 MHz			127		dB
DC PERFORMANCE
V_OS	Input offset voltage				15	±100	µV
V_OS	Input offset voltage	T_A = –40°C to +125°C				±300	µV
dV_OS/dT	Input offset voltage drift	T_A = –40°C to +125°C			0.5	±3	µV/°C
dV_OS/dT	Input offset voltage drift	OPA2625 only, T_A = –40°C to +125°C			0.6	±4
PSRR	Power-supply rejection ratio	2.7 V ≤ (V+) ≤ 5 V		100			dB
PSRR	Power-supply rejection ratio	2.7 V ≤ (V+) ≤ 5 V	T_A = –40°C to +125°C	90	120		dB
I_B	Input bias current				2	4	µA
		T_A = –40°C to +125°C				5.7
		OPA2625 only, T_A = –40°C to +125°C				6.5
dI_B/dT	Input bias current drift	T_A = –40°C to +125°C			15		nA/°C
I_OS	Input offset current				20	120	nA
		T_A = –40°C to +125°C				150
		OPA2625 only, T_A = –40°C to +125°C				200
dI_OS/dT	Input offset current drift	T_A = –40°C to +125°C			0.6		nA/°C
OPEN LOOP GAIN
A_OL	Open-loop gain	(V–) + 0.2 V < V_O< (V+) – 0.2 V, R_LOAD = 600 Ω		110			dB
		(V–) + 0.15 V < V_O< (V+) – 0.15 V, R_LOAD = 10 kΩ		114
		T_A = –40°C to +125°C	(V–) + 0.2 V < V_O< (V+) – 0.2 V, R_LOAD = 600 Ω	106	128
		T_A = –40°C to +125°C	(V–) + 0.15 V < V_O< (V+) – 0.15 V, R_LOAD = 10 kΩ	110	132
INPUT VOLTAGE
V_CM	Common-mode voltage range	T_A = –40°C to +125°C		(V–)		(V+) – 1.15	V
CMRR	Common-mode rejection ratio	(V–) < V_COM< (V+) – 1.15 V		100	117		dB
CMRR	Common-mode rejection ratio	(V–) < V_COM< (V+) – 1.15 V	T_A = –40°C to +125°C	90	115		dB
INPUT IMPEDANCE
Z_ID	Differential input impedance				27 \|\| 1.2		KΩ \|\| pF
Z_IC	Common-mode input impedance				47 \|\| 1.5		MΩ \|\| pF
OUTPUT
	Output voltage swing to the rail	R_LOAD = 600 Ω			60	80	mV
		R_LOAD = 600 Ω	T_A = –40°C to +125°C			100
		R_LOAD = 10 kΩ			20	35
		R_LOAD = 10 kΩ	T_A = –40°C to +125°C			40
I_sc	Short-circuit current				150		mA
C_LOAD	Capacitive load drive			See Typical Characteristics
MODE
V_IL	High-drive (HD) mode threshold	T_A = –40°C to +125°C		(V–)		(V–) + 0.5	V
V_IH	Low-power (LP) mode threshold	T_A = –40°C to +125°C		(V–) + 1.2		(V+)	V
I_IL	Low-level input current	T_A = –40°C to +125°C, V_MODE ≤ (V–) + 0.5 V			0.01	1	µA
I_IH	High-level input current	T_A = –40°C to +125°C, V_MODE ≥ (V–) + 1.2 V			20	30	µA
I_IH	High-level input current	OPA2625 only, T_A = –40°C to +125°C, V_MODE ≥ (V–) + 1.2 V				1	µA
POWER SUPPLY
I_Q	Quiescent current per amplifier	I_O = 0 mA, MODE connected to ground			2	2.2	mA
I_Q	Quiescent current per amplifier	I_O = 0 mA, MODE connected to ground	T_A = –40°C to +125°C			3.1	mA

6.6 Electrical Characteristics Low-Power Mode

at T_A = 25°C, V+ = 5 V, V– = 0 V, V_MODE = 5 V, V_COM = V_O = 2.5 V, gain (G) = 1, R_F = 1 kΩ, C_F = 2.7 pF, C_LOAD = 20 pF, and R_LOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
AC PERFORMANCE
GBW	Gain-bandwidth product	G = 100, V_O = 10 mV_PP			1		MHz
φ_m	Phase margin				72		Degrees
SR	Slew rate	V_O = 1-V step			4.3		V/µs
SR	Slew rate	V_O = 4-V step, G = 2			4.1		V/µs
Z_o	Open-loop output impedance	f = 1 MHz			12		Ω
DC PERFORMANCE
V_OS	Input offset voltage				0.6	3	mV
V_OS	Input offset voltage	T_A = –40°C to +125°C			0.7	3.7	mV
PSRR	Power-supply rejection ratio	2.7 V ≤ (V+) ≤ 5 V		74			dB
PSRR	Power-supply rejection ratio	2.7 V ≤ (V+) ≤ 5 V	T_A = –40°C to +125°C	70	100		dB
I_B	Input bias current					150	nA
		T_A = –40°C to +125°C			140	200
		OPA2625 only, T_A = –40°C to +125°C				250
I_OS	Input offset current					20	nA
I_OS	Input offset current	T_A = –40°C to +125°C				25	nA
OPEN LOOP GAIN
A_OL	Open-loop gain	T_A = –40°C to +125°C	(V–) + 0.2 V < V_O< (V+) – 0.2 V, R_LOAD = 600 Ω	70	100		dB
A_OL	Open-loop gain	T_A = –40°C to +125°C	(V–) + 0.15 V < V_O< (V+) – 0.15 V, R_LOAD = 10 kΩ	90	100		dB
INPUT VOLTAGE
V_CM	Common-mode voltage range	T_A = –40°C to +125°C		(V–)		(V+) – 1.15	V
CMRR	Common-mode rejection ratio	(V–) < V_COM< (V+) – 1.15 V		66	114		dB
CMRR	Common-mode rejection ratio	(V–) < V_COM< (V+) – 1.15 V	T_A = –40°C to +125°C	60	114		dB
OUTPUT
	Output voltage swing to the rail	T_A = –40°C to +125°C	R_LOAD = 600 Ω			110	mV
	Output voltage swing to the rail	T_A = –40°C to +125°C	R_LOAD = 10 kΩ			40	mV
I_sc	Short-circuit current				100		mA
POWER SUPPLY
I_Q	Quiescent current per amplifier	I_O = 0 mA, MODE connected to V+			270	320	µA
I_Q	Quiescent current per amplifier	I_O = 0 mA, MODE connected to V+	T_A = –40°C to +125°C			450	µA

6.7 Electrical Characteristics High-Drive Mode

at T_A = +25°C, V+ = 2.7 V, V– = 0 V, V_MODE = 0 V, V_COM = V_O = 1.35 V, gain (G) = 1, R_F = 1 kΩ, C_F = 2.7 pF, C_LOAD = 20 pF, and R_LOAD = 1 kΩ connected to 1.35 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
AC PERFORMANCE
	Unity gain frequency	V_O = 10 mV_PP			76		MHz
φ_m	Phase margin				45		Degrees
GBW	Gain-bandwidth product	G = 100, V_O = 10 mV_PP			120		MHz
SR	Slew rate	V_O = 1-V step, G = 2			45		V/µs
t_settle	Settling time	V_O = 1-V step, G = 2	to 0.1%		80		ns
			to 0.01%		170
			to 0.000763% (17-bit accuracy)		250
	Overshoot	V_O = 1-V step, G = 2			6%
	Undershoot	V_O = 1-V step, G = 2			5%
HD2	Second order harmonic Distortion	(V+) = 3.3 V, (V–) = 0 V, V_COM = 1.1 V, V_O = 2 V_PP	f = 10 kHz		136		dBc
			f = 100 kHz		118
			f = 1 MHz		80
HD3	Third order harmonic Distortion	(V+) = 3.3 V, (V–) = 0 V, V_COM = 1.1 V, V_O = 2 V_PP	f = 10 kHz		143		dBc
			OPA2625 only, f = 10 kHz		143
			f = 100 kHz		130
			OPA2625 only, f = 100 kHz		125
			f = 1 MHz		85
			OPA2625 only, f = 1 MHz		74
	Second order inter-modulation distortion	(V+) = 3.3 V, (V–) = 0 V, V_COM = 1.1 V, V_O = 2 V_PP, f = 1 MHz, 200-kHz tone spacing			95		dBc
	Third order inter-modulation distortion	(V+) = 3.3 V, (V–) = 0 V, V_COM = 1.1V, V_O = 1 V_PP, f = 1 MHz, 200-kHz tone spacing			104		dBc
V_N	Input noise voltage	f = 0.1 Hz to 10 Hz peak to peak			0.8		µV_PP
V_N	Input noise voltage	f = 0.1 Hz to 10 Hz rms			120		nV_RMS
V_n	Input voltage noise density	f = 10 kHz			2.5		nV/√Hz
I_n	Input current noise density	f = 10 kHz			2.8		pA/√Hz
t_OR	Overload recovery time	G = 5			35		ns
Z_o	Open-loop output impedance	f = 1 MHz			1.3		Ω
	Crosstalk	DC			150		dB
	Crosstalk	f = 1 MHz			127		dB
DC PERFORMANCE
V_OS	Input offset voltage				15	±100	µV
V_OS	Input offset voltage	T_A = –40°C to +125°C				±300	µV
dV_OS/dT	Input offset voltage drift	T_A = –40°C to +125°C			0.5	±3.1	µV/°C
dV_OS/dT	Input offset voltage drift	OPA2625 only, T_A = –40°C to +125°C			0.6	±4	µV/°C
I_B	Input bias current				2	4	µA
		T_A = –40°C to +125°C				5.7
		OPA2625 only, T_A = –40°C to +125°				6.5
dI_B/dT	Input bias current drift	T_A = –40°C to +125°C			15		nA/°C
I_OS	Input offset current				20	120	nA
		T_A = –40°C to +125°C				150
		OPA2625 only, T_A = –40°C to +125°				200
dI_OS/dT	Input offset current drift	T_A = –40°C to +125°C			80		pA/°C
OPEN-LOOP GAIN
A_OL	Open-loop gain	(V–) + 0.2 V < V_O< (V+) – 0.2 V, R_LOAD = 600 Ω		110			dB
		(V–) + 0.15 V < V_O< (V+) – 0.15 V, R_LOAD= 10 kΩ		114
		T_A = –40°C to +125°C	(V–) + 0.2 V < V_O< (V+) – 0.2 V, R_LOAD = 600 Ω	106	128
		T_A = –40°C to +125°C	(V–) + 0.15 V < V_O< (V+) – 0.15 V, R_LOAD = 10 kΩ	110	132
INPUT VOLTAGE
V_CM	Common-mode voltage range	T_A = –40°C to +125°C		(V–)		(V+) – 1.15	V
CMRR	Common-mode rejection ratio	(V–) < V_COM< (V+) – 1.15 V		100	117		dB
CMRR	Common-mode rejection ratio	(V–) < V_COM< (V+) – 1.15 V	T_A = –40°C to +125°C	90	115		dB
INPUT IMPEDANCE
Z_ID	Differential input impedance				27 \|\| 0.8		KΩ \|\| pF
Z_IC	Common-mode input impedance				47 \|\| 1.2		MΩ \|\| pF
OUTPUT
	Output voltage swing to the rail	R _LOAD = 600 Ω			60	80	mV
		R _LOAD = 600 Ω	T_A = –40°C to +125°C			100
		R _LOAD = 10 kΩ			20	35
		R _LOAD = 10 kΩ	T_A = –40°C to +125°C			40
I_SC	Short-circuit current				80		mA
C_LOAD	Capacitive load drive			See Typical Characteristics
MODE
V_IL	High-drive (HD) mode threshold	T_A = –40°C to +125°C		(V–)		(V–) + 0.5	V
V_IH	Low-power (LP) mode threshold	T_A = –40°C to +125°C		(V–) + 1.2		(V+)	V
POWER SUPPLY
I_Q	Quiescent current per amplifier	I_O = 0 mA MODE connected to ground			2	2.1	mA
I_Q	Quiescent current per amplifier	I_O = 0 mA MODE connected to ground	T_A = –40°C to +125°C			2.8	mA

6.8 Electrical Characteristics Low-Power Mode

at T_A = +25°C, V+ = 2.7 V, V– = 0 V, V_MODE = 2.7 V, V_COM = V_O = 1.35V, gain (G) = 1, R_F = 1 kΩ, C_F = 2.7 pF, C_LOAD = 20 pF, and R_LOAD = 1 kΩ connected to 1.35 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
AC PERFORMANCE
GBW	Gain-bandwidth product	G = 100, V_IN = 10 mV_PP			0.8		MHz
φ_m	Phase margin				72		Degrees
SR	Slew rate	V_O = 1 V-step, G = 2			3.7		V/µs
Z_o	Open-loop output impedance	f = 1 MHz			13		Ω
DC PERFORMANCE
V_OS	Input offset voltage				0.6	3	mV
V_OS	Input offset voltage	T_A = –40°C to +125°C			0.7	±3.6	mV
I_B	Input bias current					150	nA
		T_A = –40°C to +125°C			140	220
		OPA2625 only, T_A = –40°C to +125°				250
I_OS	Input offset current					20	nA
I_OS	Input offset current	T_A = –40°C to +125°C				25	nA
OPEN LOOP GAIN
A_OL	Open-loop gain	T_A = –40°C to +125°C	(V–) + 0.2 V < V_O< (V+) – 0.2 V, R_LOAD = 600 Ω	74	100		dB
A_OL	Open-loop gain	T_A = –40°C to +125°C	(V–) + 0.15 V < V_O< (V+) – 0.15 V, R_LOAD = 10 kΩ	84	100		dB
INPUT VOLTAGE
V_CM	Common-mode voltage range	T_A = –40°C to +125°C		(V–)		(V+) – 1.15	V
CMRR	Common-mode rejection ratio	(V–) < V_COM< (V+) – 1.15 V		66	114		dB
CMRR	Common-mode rejection ratio	(V–) < V_COM< (V+) – 1.15 V	T_A = –40°C to +125°C	60	114		dB
OUTPUT
	Output voltage swing to rail	T_A = –40°C to +125°C	R_LOAD = 600 Ω			110	mV
	Output voltage swing to rail	T_A = –40°C to +125°C	R_LOAD = 10 kΩ			40	mV
I_sc	Short-circuit current				50		mA
POWER SUPPLY
I_Q	Quiescent current per amplifier	I_O = 0 mA, MODE connected to V+			250	270	µA
I_Q	Quiescent current per amplifier	I_O = 0 mA, MODE connected to V+	T_A = –40°C to +125°C			400	µA

6.9 Switching Characteristics

at T_A = 25°C, V+ = 5 V, V– = 0 V, MODE pin connected to V– pin, gain (G) = 1 , V_COM = V_O = 2.5 V, C_LOAD = 20 pF, and R_LOAD = 1 kΩ connected to 2.5 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	UNIT
t_LP-HD	Delay time, MODE pin falling (low-power mode to high-drive mode)	Settling time to within 50 µV of final value, MODE pin = high to low (LP to HD), V_O = 3.8 V	180	ns
t_LP-HD		t_LP-HD is defined as the time taken for the quiescent current to increase from 110% of its value in LP mode to 90% of its value in HD mode.	170	ns
t_HD-LP	Delay time, MODE pin rising (high-drive mode to low-power mode)	t_HD-LP is defined as the time taken for the quiescent current to decrease from 90% of its value in HD mode to 110% of its value in LP mode.	300	ns

OPA625 OPA2625 Switch_Char_Tim_Dia_sbos688.gif

Figure 1. Switching Characteristics Timing Diagram

6.10 Typical Characteristics

At T_A = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, V_COM = V_O = 2.5 V, gain (G) = 2, R_F = 1 kΩ, C_F= 2.7 pF, C_LOAD= 20 pF, and R_LOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)

V_O = 10 mV_PP

Figure 2. Small-Signal Frequency Response for Various Gains

V_O = 10 mV_PP, G = 1

Figure 4. Small-Signal Frequency Response for Various Power Supply Voltages

V_O = 2 V_PP, G = 1

Figure 6. Large-Signal Frequency Response for Various Capacitive Loads

V_O = 10 mV_PP

Figure 8. High-Drive Mode Open-Loop Gain and Phase vs Frequency

V_O = 10 mV_PP , V_MODE = 5 V

Figure 10. Low-Power Mode Open-Loop Gain and Phase vs Frequency

Figure 12. Common-Mode Rejection Ratio vs Frequency

G = 1, C_LOAD = 1.2 nF

Figure 14. Series Resistance for Capacitive Load Stability

G = –1, V_O = 10 mV_PP

Figure 16. Overshoot vs Capacitive Load, G = –1

G = 1, V_O = 2 V_PP, R_LOAD = 600 Ω

Figure 18. Distortion vs Frequency for Various Power Supplies

G = 1, R_LOAD = 600 Ω

Figure 20. Total Harmonic Distortion vs Output Voltage for Various Frequencies

Figure 22. Voltage Noise Density vs Frequency

Figure 24. Crosstalk vs Frequency

Figure 26. Slew Rate vs Output Step Size

G = 1, V_O = 4-V step

Figure 28. Large-Signal Pulse Response

G = 1, V_O = 10-mV step

Figure 30. Small-Signal Pulse Response

V_O = 3.6-V step at t = 0 s

Figure 32. 16-Bit Negative Settling Time

V_S = ±2.75 V, G = 1

Figure 34. No Phase Reversal

V_S = ±2.75 V, G = 5

Figure 36. Negative Overload Recovery

Distribution taken from 80 amplifiers, T_A = 125°C

Figure 38. Input Offset Voltage Distribution

Distribution taken from 80 amplifiers, T_A = –40°C

Figure 40. Input Offset Voltage Distribution

Distribution taken from 83 amplifiers, T_A = –40°C to +125°C

Figure 42. Input Offset Voltage Drift Distribution

Figure 44. Input Bias Current vs Temperature

Figure 46. Input Offset Current vs Temperature

2.7 V ≤ V_S ≤ 5.5 V

Figure 48. Power-Supply Rejection Ratio vs Temperature

R_LOAD = 600 Ω

Figure 50. Open-Loop Gain vs Temperature with 600-Ω Load

6 typical units shown, V_S = ±1.35 V to ±2.75 V

Figure 52. Input Offset Voltage vs Power-Supply Voltage

Figure 54. Output Voltage vs Output Current

High-drive mode

Figure 56. High-Drive Mode Quiescent Current vs Power-Supply Voltage

MODE pin connected to V+

Figure 58. Low-Power Mode Quiescent Current vs Temperature

V_S = ±2.75 V

Figure 60. Quiescent Current When MODE transitions From High To Low

V_O = 3.8 VDC

Figure 62. Output Voltage When MODE Transitions From High To Low

V_O = 2 V_PP

Figure 3. Large-Signal Frequency Response for Various Gains

V_O = 10 mV_PP , G = 1

Figure 5. Small-Signal Frequency Response for Various Capacitive Loads

V_O = 10 mV_PP , G = 1

Figure 7. Small-Signal Frequency Response for Various Resistive Loads

Figure 9. High-Drive Mode Open-Loop Output Impedance vs Frequency

Figure 11. Low-Power Mode Open-Loop Output Impedance vs Frequency

Figure 13. Power-Supply Rejection Ratio vs Frequency

G = 1, V_O = 10 mV_PP

Figure 15. Overshoot vs Capacitive Load, G = 1

V_S = 5.5 V, V_O = 2 V_PP, R_LOAD = 600 Ω

Figure 17. Distortion vs Frequency for Various Gains

G = 2, V_O = 2 V_PP, R_LOAD = 600 Ω

Figure 19. Distortion vs Frequency for Various Power Supplies

G = 1, V_O = 2 V_PP , R_LOAD = 600 Ω

Figure 21. Total Harmonic Distortion vs Frequency for Various Loads

Figure 23. Current Noise Density vs Frequency

Figure 25. 0.1-Hz to 10-Hz Voltage Noise

Figure 27. Maximum Output Voltage vs Frequency

G = –1, V_O = 4-V step

Figure 29. Large-Signal Pulse Response

G = –1, V_O = 10-mV step

Figure 31. Small-Signal Pulse Response

V_O = 3.6-V step at t = 0 s

Figure 33. 16-Bit Positive Settling Time

V_S = ±2.75 V, G = 5

Figure 35. Positive Overload Recovery

Distribution taken from 3139 amplifiers

Figure 37. Input Offset Voltage Distribution

Distribution taken from 80 amplifiers, T_A = 85°C

Figure 39. Input Offset Voltage Distribution

7 typical units shown

Figure 41. Input Offset Voltage vs Temperature

Distribution taken from 3139 amplifiers

Figure 43. Input Bias Current Distribution

Distribution taken from 3139 amplifiers

Figure 45. Input Offset Current Distribution

Figure 47. Common-Mode Rejection Ratio vs Temperature

R_LOAD = 10 kΩ

Figure 49. Open-Loop Gain vs Temperature with 10-kΩ Load

High-drive mode, V_S = ±2.5 V

Figure 51. Input Bias Current vs Input Common-Mode Voltage

6 typical units shown, V_S = ±2.5 V

Figure 53. Input Offset Voltage vs Common-Mode Voltage

Figure 55. Short-Circuit Current vs Temperature

Figure 57. High-Drive Mode Quiescent Current vs Temperature

Low-drive mode, MODE pin connected to V+

Figure 59. Low-Power Mode Quiescent Current vs Power-Supply Voltage

V_S = ±2.75 V

Figure 61. Quiescent Current When MODE Transitions From Low To High

OPA625 powered on in high-drive mode at t = 0 s, PCB dimensions: 4 in², 2 layer, FR4

Figure 63. Warm-Up Time