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ZHCSK40E August 2019 – August 2024 OPA810

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

6.11 Typical Characteristics: ±2.375-V to ±12-V Split Supply

at V_O = 2 V_PP, R_F = 1 kΩ, R_L = 1 kΩ and T_A ≈ 25°C (unless otherwise noted)

Simulated with no output load

Figure 6-42 Open-Loop Gain and Phase vs Frequency

See Figure 8-1, gain = 2 V/V

Figure 6-44 Large-Signal Response vs Supply Voltage

See Figure 8-2, gain = –1 V/V

Figure 6-46 Harmonic Distortion vs Frequency vs Supply Voltage

Measured then fit to ideal 1/f model

Figure 6-48 Auxiliary Input Stage Voltage Noise Density vs Frequency

V_S = 10 V and 24 V

Figure 6-50 Common-Mode Rejection Ratio vs Frequency

Simulated curves, V_S = 24 V

Figure 6-52 Power Supply Rejection Ratio vs Frequency

Abs (V_{IN,Diff
(max)}) = V_S when V_S < 7 V

Figure 6-54 Input Bias Current vs Differential Input Voltage

32 units, SOIC package

Figure 6-56 Input Offset Voltage vs Ambient Temperature

27000 units, µ = 16 µV, σ = 63 µV, V_S = 24 V

Figure 6-58 Input Offset Voltage Distribution

See Figure 8-1, gain = 1 V/V, R_F = 0 Ω

Figure 6-43 Large-Signal Response vs Supply Voltage

See Figure 8-1, gain = 2 V/V

Figure 6-45 Harmonic Distortion vs Frequency vs Supply Voltage

Measured then fit to ideal 1/f model

Figure 6-47 Input Voltage Noise Density vs Frequency

Figure 6-49 Open-Loop Output Impedance vs Frequency

V_S = 5 V and 10 V

Figure 6-51 Power Supply Rejection Ratio vs Frequency

V_S = ±12 V

Figure 6-53 Input Bias Current vs Input Common-Mode Voltage

32 units, SOIC package, V_S = ±5 V

Figure 6-55 Quiescent Current vs Ambient Temperature

27000 units, µ = 3.82 mA, σ = 17 µA, V_S = 24 V

Figure 6-57 Quiescent Current Distribution

–40°C to +125°C fit, 32 units, µ = –0.15 µV/°C, σ = 2.5 µV/°C

Figure 6-59 Input Offset Voltage Drift Distribution