米6体育平台手机版

SBOS303D June 2004 – December 2016 OPA820

PRODUCTION DATA.

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

D|8
DBV|5

散热焊盘机械数据 (封装 | 引脚)

订购信息

12 Layout

12.1 Layout Guidelines

Achieving optimum performance with a high-frequency amplifier such as the OPA820 device requires careful attention to board layout parasitics and external component types. This section lists recommendations to optimize performance.

12.1.1 Minimizing Parasitic Capacitance

Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability. On the noninverting input, parasitic capacitance can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins must be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes must be unbroken elsewhere on the board.

12.1.2 Minimizing Distance from Power Supply to Decoupling Capacitors

Minimize the distance, less than 0.25 inches, from the power-supply pins to high-frequency 0.1-µF decoupling capacitors. At the device pins, the ground and power-plane layout must not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections must always be decoupled with these capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, must also be used on the main supply pins. Place these capacitors somewhat farther from the device. These capacitors can be shared among several devices in the same area of the PCB.

12.1.3 Selecting and Placing External Components

Careful selection and placement of external components preserves the high-frequency performance of the OPA820 device. Resistors must be a very-low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially leaded resistors can also provide good high-frequency performance. Again, keep the leads and PCB trace length as short as possible. Never use wire-wound type resistors in a high-frequency application. Because the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, must also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values greater than 1.5 kΩ, this parasitic capacitance can add a pole, a zero, or both below 500 MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load-driving considerations. A good starting point for design is to set R_G || R_F = 200 Ω. Using this setting automatically keeps the resistor noise terms low, and minimizes the effect of the parasitic capacitance.

12.1.4 Connecting Other Wideband Devices

Connections to other wideband devices on the board can be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) must be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set R_S from the plot of Figure 15 (±5 V) and Figure 42 (5 V). Low parasitic capacitive loads (<5 pF) may not require an R_S because the OPA820 device is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an R_S are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not necessary onboard, and in fact, a higher impedance environment improves distortion as shown in Figure 7 and Figure 36. With a characteristic board-trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA820 device is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and input impedance of the destination device; this total effective impedance must be set to match the trace impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of Figure 15 (±5 V) and Figure 42 (5 V) which does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, some signal attenuation occurs because of the voltage divider formed by the series output into the terminating impedance.

12.1.5 Socketing

TI does not recommend socketing a high-speed part like the OPA820 device. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make achieving a smooth, stable frequency response almost impossible. The best results are obtained by soldering the OPA820 device onto the board.

12.2 Layout Example

Figure 68. OPA820 Layout Example