The OPA835 and OPA2835 devices include a power-down mode. Under logic control, the amplifiers can switch from normal operation to a standby current of < 1.5 µA. When the PD pin is connected high, the amplifier is active. Connecting PD pin low disables the amplifier and places the output in a high-impedance state. When the amplifier is configured as a unity-gain buffer, the output stage is in a high dc-impedance state. To protect the input stage of the amplifier, the devices use internal, back-to-back ESD diodes between the inverting and noninverting input pins. This configuration creates a parallel low-impedance path from the amplifier output to the noninverting pin when the differential voltage between the pins exceeds a diode voltage drop. When the op amp is configured in other gains, the feedback (RF) and gain (RG) resistor network forms a parallel load.

The PD pin must be actively driven high or low and must not be left floating. If the power-down mode is not used, PD must be tied to the positive supply rail.

PD logic states are TTL with reference to the negative supply rail, V_S–. When the op amp is powered from a single-supply and ground, driven from logic devices with similar V_DD voltages to the op amp do not require any special consideration. When the op amp is powered from a split supply, with V_S– below ground, an open-collector type of interface with a pullup resistor is more appropriate. Pullup resistor values must be lower than 100 kΩ. Additionally, the drive logic must be negated due to the inverting action of an open-collector gate.