ZHCSGM4D August   2017  – September 2024 OPA838

PRODMIX  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics VS = 5 V
    6. 6.6 Electrical Characteristics VS = 3 V
    7. 6.7 Typical Characteristics: VS = 5 V
    8. 6.8 Typical Characteristics: VS = 3 V
    9. 6.9 Typical Characteristics: Over Supply Range
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Common-Mode Voltage Range
      2. 7.3.2 Output Voltage Range
      3. 7.3.3 Power-Down Operation
      4. 7.3.4 Trade-Offs in Selecting The Feedback Resistor Value
      5. 7.3.5 Driving Capacitive Loads
    4. 7.4 Device Functional Modes
      1. 7.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 7.4.2 Single-Supply Operation (2.7 V to 5.4 V)
      3. 7.4.3 Power Shutdown Operation
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Noninverting Amplifier
      2. 8.1.2 Inverting Amplifier
      3. 8.1.3 Output DC Error Calculations
      4. 8.1.4 Output Noise Calculations
    2. 8.2 Typical Applications
      1. 8.2.1 High-Gain Differential I/O Designs
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Transimpedance Amplifier
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 开发支持
        1. 9.1.1.1 TINA-TI™ 仿真软件(免费下载)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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订购信息

High-Gain Differential I/O Designs

A high-gain differential-to-differential I/O circuit can be used to drive a second-stage FDA or a differential-to-single-ended stage. This circuit is frequently used in applications where high input impedance is required (for example, if the source cannot be loaded). Figure 8-3 illustrates an example design where the differential gain is 41 V/V. An added element between the two RG resistors increases the noise gain for the common-mode feedback. Make sure to provision for the added element; otherwise, a decompensated VFA (such as the OPA838) often oscillates. With only the RG elements in the differential I/O design, the common-mode feedback is unity-gain and often causes high-frequency, common-mode oscillations. To resolve this issue, split the RG elements in half and add a low-impedance path, such as a capacitor or a DC reference, between the two RG values.

OPA838 High-Gain Differential I/O StageFigure 8-4 High-Gain Differential I/O Stage

Integrated results are available, but the OPA838 provides a low-power, high-frequency result. For best CMRR performance, match the resistors. A good rule is CMRR is approximately equal to the resistor tolerance; therefore, a 0.1% tolerance provides approximately 60-dB CMRR.