ZHCSK39C August   2019  – August 2020 OPA862

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VS = ±2.5 V to ±5 V
    6. 6.6 Typical Characteristics: VS = ±5 V
    7. 6.7 Typical Characteristics: VS = ±2.5 V
    8. 6.8 Typical Characteristics: VS = 1.9 V, –1.4 V
    9. 6.9 Typical Characteristics: VS = 1.9 V, –1.4 V to ±5 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and ESD Protection
      2. 7.3.2 Anti-Phase Reversal Protection
      3. 7.3.3 Precision and Low Noise
    4. 7.4 Device Functional Modes
      1. 7.4.1 Split-Supply Operation (±1.5 V to ±6.3 V)
      2. 7.4.2 Single-Supply Operation (3 V to 12.6 V)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Single-Ended-to-Differential Gain of 4 V/V
    2. 8.2 Typical Applications
      1. 8.2.1 Single-Ended to Differential with 2.5-V Output Common-Mode Voltage
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Transimpedance Amplifier Configuration
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 DC Level-Shifting
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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6.5 Electrical Characteristics: VS = ±2.5 V to ±5 V

TA ≈ 25°C, A1 input common-mode voltage (VCM) = midsupply, VREF = midsupply, RF (connected between
VOUT+ and VFB) = 0 Ω, RG = open, differential gain (G) = 2 V/V, RL (differential load) = 2 kΩ, RREF = 0 Ω, and
VS = ±5 V for VOD = 10 VPP condtions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Differential small-signal bandwidth VOD = 20 mVPP 44 MHz
VOD = 20 mVPP, G = 4 V/V, RF = 700 Ω 48
VOD = 20 mVPP, G = –2 V/V, RF = 700 Ω 48
LSBW Differential large-signal bandwidth VOD = 1 VPP 42 MHz
VS = ±2.5 V, VOD = 5 VPP 14
VOD = 10 VPP 7.5
GBWP Differential gain-bandwidth product VOD = 40 mVPP, G = 200 V/V,
RF = 700 Ω		 400 MHz
Bandwidth for 0.1-dB flatness VOD = 20 mVPP, G = 2 V/V 6.5 MHz
Output balance (ΔVOD / ΔVOCM) VOD = 5 VPP, f = 1 MHz 41 dB
SR Slew rate(1) (20% – 80%) VOD = 10 VPP 140 V/µs
Overshoot, undershoot VOD = 10-V step 0.2%
tr, tf Rise and fall time VOD = 200-mV step 8.5 ns
Settling time To 0.0015% of final value,
VOD = 10-V step		 100 ns
Input overdrive recovery VIN = VS ± 0.5 V, VREF = midsupply 100 ns
Output overdrive recovery G = –4 V/V, VOD = 2x overdrive 120 ns
HD2 Second-order harmonic distortion VOD = 10 VPP, f = 15 kHz –133 dBc
VOD = 10 VPP, f = 50 kHz –122
VOD = 10 VPP, f = 350 kHz –110
HD3 Third-order harmonic distortion VOD = 10 VPP, f = 15 kHz –148 dBc
VOD = 10 VPP, f = 50 kHz –140
VOD = 10 VPP, f = 350 kHz –110
en Differential output noise f ≥ 10 kHz 8.3 nV/√Hz
Input voltage noise of A1 and A2 f ≥ 5 kHz 2.3
ei Input current noise of A1 f ≥ 100 kHz 0.7 pA/√Hz
Input current noise of A2 f ≥ 100 kHz 0.9
DC PERFORMANCE
VOS Differential output offset voltage ±50 ±700 µV
Input offset voltage for A1, A2 ±50 ±325
Differential output offset drift TA = 0°C to 85°C,
TA = –40°C to 125°C		 SOIC ±1.5 ±9 µV/°C
WSON ±1.5 ±7
Input offset voltage drift for A1, A2 TA = 0°C to 85°C,
TA = –40°C to 125°C		 SOIC ±0.5 ±3
WSON ±0.5 ±2.5
IB Input bias current, A1 1 3.1 µA
Input bias current, A2 VREF pin ±5 ±90 nA
Input bias current drift, A1 TA = –40°C to 125°C 13 nA/°C
Input bias current drift, A2 VREF pin, TA = –40°C to 125°C ±65 pA/°C
IOS Input offset current, A1 ±4 ±110 nA
G Differential gain 2 V/V
Differnetial gain error ±0.1 ±0.25 %
Differential gain error drift TA = –40°C to 125°C ±0.02 ppm/°C
RINT Internal resistors 700 Ω
INPUT
CMIR Input common-mode range, A1 VS– + 0.5 VS+ – 1.1 V
VREF pin common-mode range VS– + 1.3 VS+ – 1.1
ΔVOS (2) at CMIR specification, A1 VCM = VS+ – 1.1 V and
VCM = VS– + 0.5 V		 ±25 µV
ΔVOS (2) at CMIR specification VREF = VS+ – 1.1 V and
VREF = VS– + 1.3 V		 ±50 µV
CMRR Common-mode rejection ratio CMRR = VOD / VIN, VIN = VREF,
VCM = ±1 V, RREF = 0 Ω		 100 120 dB
Input impedance common-mode, A1 325 || 0.6 MΩ || pF
Input impedance differential-mode, A1 35 || 1.9 kΩ || pF
Input impedance, A2 VREF pin 2.3 || 3.5 GΩ || pF
OUTPUT
VOL Output voltage range low Each output, single-ended VS– + 0.15 VS– + 0.25 V
VOH Output voltage range high Each output, single-ended VS+ – 0.25 VS+ – 0.15 V
Linear output current VS = ±5 V, VOD = ±2.65 V, ∆VOCM < ±10 mV relative to no-load condition 40 60 mA
POWER SUPPLY
VS Specified operating voltage Single-supply referred to GND 3 10 12.6 V
IQ Quiescent current VS = ±5 V, TA = 25°C 2.8 3.1 3.3 mA
Quiescent current drift VS = ±5 V, TA = –40°C to 125°C 9 µA/°C
PSRR Power-supply rejection ratio VIN = VREF = 0 V, ΔVS = 2 V 105 115 dB
POWER DOWN
Disable voltage threshold Disabled above specified voltage VS– + 1.5 V
Enable voltage threshold Enabled below specified voltage VS– + 1 V
Disable pin bias current –10 10 nA
Power-down quiescent current 12 20 µA
Turn-on time delay 1.3 µs
Turn-off time delay 2.5 µs
(1) Average of rising and falling slew rate.
(2) ΔVOS = VOS at specified CMIR VCM – VOS at midsupply VCM.
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