ZHCSOS5F May   2022  – October 2024 OPA2863A , OPA863A

PRODMIX  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information OPA863A
    5. 6.5  Thermal Information OPA2863A
    6. 6.6  Electrical Characteristics VS = ±5 V
    7. 6.7  Electrical Characteristics VS = 3 V
    8. 6.8  Typical Characteristics: VS = ±5 V
    9. 6.9  Typical Characteristics: VS = 3 V
    10. 6.10 Typical Characteristics: VS = 3 V to 10 V
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Stage
      2. 7.3.2 Output Stage
        1. 7.3.2.1 Overload Power Limit
      3. 7.3.3 ESD Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Active Filters
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Low-Power SAR ADC Driver and Reference Buffer
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DBV|5
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.7 Electrical Characteristics VS = 3 V

at G = 1 V/V, RF = 0 Ω for G = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ connected to 1 V, input and output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 20 mVPP, G = 1 85 MHz
GBWP Gain-bandwidth product 50 MHz
LSBW Large-signal bandwidth VOUT = 1 VPP 23 MHz
Bandwidth for 0.1-dB flatness VOUT = 20 mVPP 10 MHz
SR Slew rate VOUT = 1-V step 53 V/µs
Rise, fall time VOUT = 200-mV step 10 ns
Settling time To 0.1%, VOUT = 1-V step 58 ns
To 0.01%, VOUT = 1-V step 90
Overshoot VOUT = 1-V step 2 %
Undershoot VOUT = 1-V step 16 %
Overdrive recovery time G = –1, 0.5-V overdrive beyond supplies 85 ns
G = 1, 0.5-V overdrive beyond supplies 130
HD2 Second-order harmonic distortion f = 20 kHz, VOUT = 1 VPP –123 dBc
HD3 Third-order harmonic distortion f = 20 kHz, VOUT = 1 VPP –132 dBc
HD2 Second-order harmonic distortion f = 100 kHz, VOUT = 1 VPP –109 dBc
HD3 Third-order harmonic distortion f = 100 kHz, VOUT = 1 VPP –129 dBc
eN Input voltage noise 6.3 nV/√Hz
iN Input current noise 0.5 pA/√Hz
Closed-loop output impedance f = 1 MHz 0.2 Ω
Channel-to-channel crosstalk f = 1 MHz, VOUT = 1 VPP –120 dBc
DC PERFORMANCE
AOL Open-loop voltage gain VOUT = 1 V to 2 V 104 123 dB
VOS Input-referred offset voltage –95 ±10 95 μV
Input offset voltage drift TA = –40°C to +125°C –1.2 ±0.3 1.2 μV/°C
Input bias current TA ≅ 25°C 0.3 0.73 µA
TA = –40°C to +85°C 1.2
TA = –40°C to +125°C 1.56
Input bias current drift TA = –40°C to +125°C ±3 nA/°C
Input offset current –30 ±10 30 nA
INPUT
Input common-mode voltage VS––0.2 VS++0.2 V
CMRR Common-mode rejection ratio VCM = VS– – 0.2 V to VS+ – 1.6 V 92 115 dB
Input impedance common-mode 360 || 0.9 MΩ || pF
Input impedance differential mode 200 || 0.5 kΩ || pF
OUTPUT
VOL Output voltage, low TA ≅ 25°C VS–+ 0.13 VS–+ 0.15 V
TA = –40°C to +125°C VS–+ 0.13 VS–+ 0.16
VOH Output voltage, high TA ≅ 25°C VS+–0.15 VS+–0.13 V
TA = –40°C to +125°C VS+–0.15 VS+–0.13
Linear output drive
(sourcing and sinking)		 VOUT = ±0.7 V, ΔVOS < 1 mV(1) 23 33 mA
Short-circuit current 45 mA
POWER SUPPLY
IQ Quiescent current per amplifier TA ≈ 25°C 770 890 µA
TA = –40°C to +125°C 995
PSRR Power-supply rejection ratio ΔVS = ±1 V(2) 100 120 dB
POWER DOWN
Enable voltage threshold Specified on when > VS+ – 0.5 V 2.5 V
Disable voltage threshold Specified off when < VS+ – 1.5 V 1.5 V
Power-down quiescent current per channel VPD ≤ VS+ – 1.5 V 8.5 20 µA
VPD ≤ VS+ – 1.5 V, TA = –40°C to +125°C 30
Power-down pin bias current 1 2.5 µA
Turn-on time delay 8 µs
Turn-off time delay 3.5 µs
AUXILIARY INPUT STAGE
Gain-bandwidth product 50 MHz
Input voltage noise 6.3 nV/√Hz
Input current noise 0.5 pA/√Hz
Input-referred offset voltage –95 ±10 95 μV
Input bias current TA ≅ 25°C 0.2 0.6 µA
TA = –40°C to +125°C 0.4 1.2
Common-mode rejection ratio VCM = 2.1 V to 3.2 V 115 dB
Power supply rejection ratio ΔVS = ±0.6 V 115 dB
(1) Change in input offset voltage from no-load condition.
(2)
Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and –PSRR.
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