8.5.1 Writing and Reading

Accessing a specific register on the OPT3001-Q1 device is accomplished by writing the appropriate register address during the I²C transaction sequence. Refer to Table 6 for a complete list of registers and their corresponding register addresses. The value for the register address (as shown in Figure 23) is the first byte transferred after the slave address byte with the R/W bit low.

1.

NOINDENT:

The value of the slave address byte is determined by the ADDR pin setting; see Table 1.

Figure 23. Setting the I²C Register Address

Writing to a register begins with the first byte transmitted by the master. This byte is the slave address with the R/W bit low. The OPT3001-Q1 device then acknowledges receipt of a valid address. The next byte transmitted by the master is the address of the register that data are to be written to. The next two bytes are written to the register addressed by the register address. The OPT3001-Q1 device acknowledges receipt of each data byte. The master may terminate the data transfer by generating a start or stop condition.

When reading from the OPT3001-Q1 device, the last value stored in the register address by a write operation determines which register is read during a read operation. To change the register address for a read operation, a new partial I²C write transaction must be initiated. This partial write is accomplished by issuing a slave address byte with the R/W bit low, followed by the register address byte and a stop command. The master then generates a start condition and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register address. This byte is followed by an acknowledge from the master; then the slave transmits the least significant byte. The master acknowledges receipt of the data byte. The master may terminate the data transfer by generating a not-acknowledge after receiving any data byte, or by generating a start or stop condition. If repeated reads from the same register are desired, continually sending the register address bytes is not necessary; the OPT3001-Q1 device retains the register address until that number is changed by the next write operation.

Figure 24 and Figure 25 show the write and read operation timing diagrams, respectively. Note that register bytes are sent most significant byte first, followed by the least significant byte.

1.

NOINDENT:

The value of the slave address byte is determined by the setting of the ADDR pin; see Table 1.

Figure 24. I²C Write Example

1.

NOINDENT:

The value of the slave address byte is determined by the ADDR pin setting; see Table 1.

2.

NOINDENT:

An ACK by the master can also be sent.

Figure 25. I²C Read Example