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ZHCSF44A May 2016 – June 2016 OPT3002

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

DNP|6
- MPDS564B

散热焊盘机械数据 (封装 | 引脚)

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6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

		MIN	MAX	UNIT
Voltage	VDD to GND	–0.5	6	V
Voltage	SDA, SCL, INT, and ADDR to GND	–0.5	6	V
Current into any pin			10	mA
Temperature	Junction, T_J		150	°C
Temperature	Storage, T_stg	–65	150⁽²⁾	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Long exposure to temperatures higher than 105°C can cause package discoloration, spectral distortion, and measurement inaccuracy.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
Operating power-supply voltage		1.6		3.6	V
Operating temperature		–40		85	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		OPT3002	UNIT
		DNP (USON)
		6 PINS
R_θJA	Junction-to-ambient thermal resistance	71.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	45.7	°C/W
R_θJB	Junction-to-board thermal resistance	42.2	°C/W
ψ_JT	Junction-to-top characterization parameter	2.4	°C/W
ψ_JB	Junction-to-board characterization parameter	42.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	17.0	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at T_A = 25°C, V_DD = 3.3 V, 800-ms conversion time (CT = 1)⁽³⁾, automatic full-scale range (RN[3:0] = 1100b⁽³⁾), 505-nm LED stimulus, and normal-angle incidence of light (unless otherwise specified)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
OPTICAL
	Peak irradiance spectral responsivity				505		nm
	Resolution (LSB) at 505 nm	Lowest full-scale range (FSR), RN[3:0] = 0000b⁽³⁾			1.2		nW/cm²⁽¹⁾
	Full-scale illuminance at 505 nm				10.064		mW/cm²⁽¹⁾
	Measurement output result	505-nm LED stimulus, FSR setting = 628,992 (nW/cm²), 153.6 (nW/cm²) per ADC code (RN[3:0] = 0111)⁽³⁾			384,000		nW/cm²⁽¹⁾
					2500		ADC codes
		2 klux white LED stimulus, FSR setting = 628,992 (nW/cm²), 153.6 (nW/cm²) per ADC code (RN[3:0] = 0111)⁽³⁾⁽⁴⁾		2250	2500	2750	ADC codes
	Relative accuracy between gain ranges⁽²⁾				0.2%
	Infrared response (850 nm) relative to response at 505 nm⁽⁴⁾				20%
	Linearity	Input illuminance > 5000 nW/cm²			2%
	Linearity	Input illuminance < 5000 nW/cm²			5%
	Dark condition, ADC output	Lowest FSR, RN[3:0] = 0000b, 4914 (nW/cm²), 1.2 (nW/cm²) per ADC code			0	3	ADC codes
	Half-power angle	50% of full-power reading			60		Degrees
PSRR	Power-supply rejection ratio	VDD at 3.6 V and 1.6 V			0.1		%/V⁽⁵⁾
POWER SUPPLY
V_I²C	I²C pullup resistor operating range	I²C pullup resistor, VDD ≤ V_I²C		1.6		5.5	V
I_Q	Quiescent current	Dark	Active, VDD = 3.6 V		1.8	2.5	µA
		Dark	Shutdown (M[1:0] = 00)⁽³⁾, VDD = 3.6 V		0.3	0.47
		Full-scale range	Active, VDD = 3.6 V		3.7
		Full-scale range	Shutdown, (M[1:0] = 00)⁽³⁾		0.4
POR	Power-on-reset threshold	T_A = 25°C			0.8		V
DIGITAL
	I/O pin capacitance				3		pF
	Total integration time⁽⁶⁾	(CT = 1)⁽³⁾, 800-ms mode, fixed FSR		720	800	880	ms
	Total integration time⁽⁶⁾	(CT = 0)⁽³⁾, 100-ms mode, fixed FSR		90	100	110	ms
V_IL	Low-level input voltage (SDA, SCL, and ADDR)			0		0.3 × VDD	V
V_IH	High-level input voltage (SDA, SCL, and ADDR)			0.7 × VDD		5.5	V
I_IL	Low-level input current (SDA, SCL, and ADDR)				0.01	0.25⁽⁷⁾	µA
V_OL	Low-level output voltage (SDA and INT)	I_OL = 3 mA				0.32	V
I_ZH	Output logic high, high-Z leakage current (SDA, INT)	At VDD pin			0.01	0.25⁽⁷⁾	µA

(1) All nW/cm² units assume a 505-nm stimulus. To scale the LSB size, full-scale, and results at other wavelengths, see the Compensation for the Spectral Response section.

(2) Characterized by measuring fixed near-full-scale light levels on the higher adjacent full-scale range setting.

(3) Refers to a control field within the configuration register.

(4) Tested with the white LED calibrated to 2 klux and an 850-nm LED.

(5) PSRR is the percent change of the measured optical power output from its current value, divided by the change in power-supply voltage, as characterized by results from the 3.6-V and 1.6-V power supplies.

(6) The conversion time, from start of conversion until data are ready to be read, is the integration time plus 3 ms.

(7) The specified leakage current is dominated by the production test equipment limitations. Typical values are much smaller.

6.6 Timing Requirements⁽¹⁾

		MIN	TYP	MAX	UNIT
I²C FAST MODE
f_SCL	SCL operating frequency	0.01		0.4	MHz
t_BUF	Bus free time between stop and start	1300			ns
t_HDSTA	Hold time after repeated start	600			ns
t_SUSTA	Setup time for repeated start	600			ns
t_SUSTO	Setup time for stop	600			ns
t_HDDAT	Data hold time	20		900	ns
t_SUDAT	Data setup time	100			ns
t_LOW	SCL clock low period	1300			ns
t_HIGH	SCL clock high period	600			ns
t_RC and t_FC	Clock rise and fall time			300	ns
t_RD and t_FD	Data rise and fall time			300	ns
t_TIMEO	Bus timeout period. If the SCL line is held low for this duration of time, then the bus state machine is reset.		28		ms
I²C HIGH-SPEED MODE
f_SCL	SCL operating frequency	0.01		2.6	MHz
t_BUF	Bus free time between stop and start	160			ns
t_HDSTA	Hold time after repeated start	160			ns
t_SUSTA	Setup time for repeated start	160			ns
t_SUSTO	Setup time for stop	160			ns
t_HDDAT	Data hold time	20		140	ns
t_SUDAT	Data setup time	20			ns
t_LOW	SCL clock low period	240			ns
t_HIGH	SCL clock high period	60			ns
t_RC and t_FC	Clock rise and fall time			40	ns
t_RD and t_FD	Data rise and fall time			80	ns
t_TIMEO	Bus timeout period. If the SCL line is held low for this duration of time, then the bus state machine is reset.		28		ms

(1) All timing parameters are referenced to low and high voltage thresholds of 30% and 70%, respectively, of the final settled value.

Figure 1. I²C Detailed Timing Diagram

6.7 Typical Characteristics

at T_A = 25°C, V_DD = 3.3 V, 800-ms conversion time (CT = 1), automatic full-scale range (RN[3:0] = 1100b), white LED, and normal-angle incidence of light (unless otherwise specified)