The device has an interrupt reporting system that allows the processor connected to the I²C bus to go to sleep, or otherwise ignore the device results, until a user-defined event occurs that requires possible action. Alternatively, this same mechanism can also be used with any system that can take advantage of a single digital signal that indicates whether the light is above or below levels of interest.

The INT pin has an open-drain output, which requires the use of a pull-up resistor. This open-drain output allows multiple devices with open-drain INT pins to be connected to the same line, thus creating a logical NOR or AND function between the devices. The polarity of the INT pin can be controlled by the INT_POL.

There are two major types of interrupt reporting mechanism modes: latched window comparison mode and transparent hysteresis comparison mode. The configuration register LATCH controls which of these two modes is used. Table 8-1 and Figure 8-4 summarize the function of these two modes. Additionally, the INT pin can either be used to indicate a fault in one of these modes (INT_CFG=0) or to indicate a conversion completion (INT_CFG >0). This is shown in Table 8-2.

Figure 8-4 Interrupt Pin Status (for INT_CFG=0 setting) and Register Flag Behavior

The THRESHOLD_H, THRESHOLD_L, LATCH and FAULT_COUNT registers control the interrupt behavior. The LATCH field setting allows a choice between the latched window mode and transparent hysteresis mode as shown in the table. Interrupt reporting can be observed on INT pin (for SOT-5X3 variant only), the FLAG_H, and the FLAG_L registers.

Results from comparing the current sensor measurements with THRESHOLD_H and THRESHOLD_L registers are referred to as fault events. The calculations to set these registers can be found in Threshold Detection Calculations. The FAULT_COUNT register dictates the number of continuous fault events required to trigger an interrupt event and subsequently change the state of the interrupt reporting mechanisms. For example, with a FAULT_COUNT value of 2 corresponding to 4 fault counts, the INT pin (for SOT-5X3 variant only), FLAG_H and FLAG_L states shown in the table are not realized unless 4 consecutive measurements are taken that satisfy the fault condition.

INT pin function (for SOT-5X3 variant only) listed in Table 8-1is valid only when INT_CFG=0. The INT pin function can be changed to indicate an end of conversion or FIFO full state as shown in Table 8-2. The FLAG_H and FLAG_L registers continue to behave as listed in Table 8-1 even while INT_CFG>0. The polarity of the INT pin is controlled by the INT_POL register.