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SBAS703A June 2015 – June 2015 OPT9221

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

ZVM|256
- MPBGAI1A

散热焊盘机械数据 (封装 | 引脚)

订购信息

sbas703a_oa

6 Specifications

6.1 Absolute Maximum Ratings

at GND = 0 V and all voltages related to ground (unless otherwise noted)⁽¹⁾ ⁽²⁾

		MIN	MAX	UNIT
Core voltage	VCCINT	–0.5	1.8	V
I/O voltage	VCCIO	–0.5	3.75	V
PLL digital supply	VCCD_PLL	–0.5	4.5	V
PLL Analog supply	VCCA	–0.5	3.75	V
Input voltage at input pins, V_I		–0.5	4.2	V
Output current from output pins, I_OUT		–25	40	mA
Operating junction temperature, T_J		–40	125	°C
Storage temperature range, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the device ground.

6.2 ESD Ratings

			MIN	MAX	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾		2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾		500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

at GND = 0 V and all voltages related to ground (unless otherwise noted)

			MIN	NOM	MAX	UNIT
VCCINT	Core voltage		1.15	1.2	1.25	V
VCCIO	I/O voltage	1.8-V operation	1.71	1.8	1.89	V
		2.5-V operation	2.375	2.5	2.625
		3.3-V operation	3.135	3.3	3.465	V
VCCD_PLL	PLL digital supply		1.16	1.2	1.24	V
VCCA	PLL Analog supply		2.375	2.5	2.625	V
V_I	Input voltage at input pins		–0.3		VCCIO⁽¹⁾ + 0.3	V
T_J	Operating junction temperature		0		85	°C
t_RAMP	Power-supply ramp time		50		3000	µs

(1) VCCIO is the corresponding bank voltage

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		OPT9221	UNIT
		ZVM (NFBGA)
		256 BALLS
R_θJA	Junction-to-ambient thermal resistance	30.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	7.6
R_θJB	Junction-to-board thermal resistance	16.0

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

PARAMETER		MIN	MAX	UNIT
1.8-V CMOS I/Os
V_IH	High-level input threshold	0.65 × VCCIO⁽¹⁾		V
V_IL	Low-level input threshold		0.35 × VCCIO	V
V_OH	High-level output voltage	VCCIO – 0.45		V
V_OL	Low-level output voltage		0.45	V
I_lkg	Input pin leakage current⁽²⁾	–10	10	µA
I_OH	High-level output current		–2	mA
I_OL	Low-level output current		2	mA
3.3-V LVCMOS I/Os
V_IH	High-level input voltage	1.7		V
V_IL	Low-level input voltage		0.8	V
V_OH	High-level output voltage	VCCIO – 0.2		V
V_OL	Low-level output voltage		0.2	V
I_lkg	Input pin leakage current⁽²⁾	–10	10	µA
I_OH	High-level output current		–2	mA
I_OL	Low-level output current		2	mA

(1) VCCIO is the corresponding bank voltage.

(2) For, 0 < Input voltage < VCCIO.

6.6 Timing Requirements

PARAMETER			MIN	TYP	MAX	UNIT
SYSCLK_IN	System input clock frequency			6		MHz
				12		MHz
				24		MHz
				48		MHz
	Duty cycle		40%		60%
SYSCLK_FREQ	Internal system clock frequency			48		MHz
VD_IN	VD_IN pulse duration		40			ns
RESET	RESET pulse duration		40			ns
I²C clock	Slave I²C interface clock frequency			400		KHz
I²C clock	Master I²C interface clock frequency			400		KHz
	Sensor I²C interface clock frequency			400		KHz
PARALLEL CMOS MODE (Assuming default OP_CLK polarity)
t_su	Data setup time	Data valid to zero crossing of CLKOUT	5			ns
t_h	Data hold time	Zero crossing of CLKOUT to data becoming invalid	20			ns

Figure 1. Timing Diagram