In a normal set up shown in Figure 8-1, the enable pin and V_REF2 are shorted together and tied to a 200-kΩ resistor, and a reference voltage equal to V_REF1 plus the FET threshold voltage is established. This reference voltage is used to help pass lows from one side to another more effectively while still separating the different pull up voltages on both sides.

Figure 8-1 Normal Setup

Care should be taken to make sure V_REF2 has an external resistor tied between it and V_CC2. If V_REF2 is tied directly to the V_CC2 rail without a resistor, then there is no external resistance from the V_CC2 to V_CC1 to limit the current such as in Figure 8-2. This effectively looks like a low impedance path for current to travel through and potentially break the pass FET if the current flowing through the pass FET is larger than the absolute maximum continuous channel current specified in section 6.1. The continuous channel current is larger with a higher voltage difference between V_CC1 and V_CC2.

Figure 8-2 shows an improper set up. If V_CC2 is larger than V_CC1 but less than V_th, the impedance between V_CC1 and V_CC2 is high resulting in a low drain to source current, which does not cause damage to the device. Concern arises when V_CC2 becomes larger than V_CC1 by V_th. During this event, the NFET turns on and begin to conduct current. This current is dependent on the gate to source voltage and drain to source voltage.

Figure 8-2 Abnormal Setup