ZHCSNI7H
September 2006 – March 2021
PCA9534
PRODUCTION DATA
1
特性
2
说明
3
Revision History
4
Description (Continued)
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Resistance Characteristics
7.5
Electrical Characteristics
7.6
I2C Interface Timing Requirements
7.7
Switching Characteristics
7.8
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Functional Block Diagram
9.2
Device Functional Modes
9.2.1
Power-On Reset
9.2.2
I/O Port
9.2.3
Interrupt Output ( INT)
9.2.3.1
Interrupt Errata
9.2.3.1.1
Description
9.2.3.1.2
System Impact
9.2.3.1.3
System Workaround
9.3
Programming
9.3.1
I2C Interface
9.3.2
Register Map
9.3.2.1
Device Address
9.3.2.2
Control Register And Command Byte
9.3.2.3
Register Descriptions
9.3.2.4
Bus Transactions
9.3.2.4.1
Writes
9.3.2.4.2
Reads
10
Application Information Disclaimer
10.1
Application Information
10.1.1
Typical Application
10.1.1.1
Design Requirements
10.1.1.1.1
Minimizing ICC When The I/O Controls Leds
11
Power Supply Recommendations
11.1
Power-On Reset Requirements
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
Support Resources
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
DGV|16
MPDS006C
DW|16
MSOI003I
PW|16
MPDS361A
DB|16
MPDS507A
RGV|16
MPQF121F
散热焊盘机械数据 (封装 | 引脚)
DW|16
QFND313D
RGV|16
QFND107G
订购信息
zhcsni7h_oa
zhcsni7h_pm
9.1
Functional Block Diagram
Pin numbers shown are for DB, DGV, DW, or PW package.
All I/Os are set to inputs at reset.
Figure 9-1
Logic Diagram (Positive Logic)
At power-on reset, all registers return to default values.
Figure 9-2
Simplified Schematic of P0 to P7
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