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ZHCSNJ3I October 2005 – June 2022 PCA9546A

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

DGV|16
- MPDS006C
DW|16
- MSOI003I
PW|16
- MPDS361A
RGY|16
- MPQF115G
D|16
- MPDS178G
RGV|16
- MPQF121F

散热焊盘机械数据 (封装 | 引脚)

DW|16
- QFND313D
RGY|16
- QFND040P
RGV|16
- QFND107G

订购信息

10.1 Power-On Reset Requirements

In the event of a glitch or data corruption, PCA9546A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 10-1 and Figure 10-2.

Figure 10-1 V_CC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To V_CC

Figure 10-2 V_CC Is Lowered Below The Por Threshold, Then Ramped Back Up To V_CC

Table 10-1 specifies the performance of the power-on reset feature for PCA9546A for both types of power-on reset.

Table 10-1 Recommended Supply Sequencing And Ramp Rates⁽¹⁾

PARAMETER			MIN	MAX	UNIT
V_{CC_FT}	Fall rate	See Figure 10-1	1	100	ms
V_{CC_RT}	Rise rate	See Figure 10-1	0.01	100	ms
V_{CC_TRR_GND}	Time to re-ramp (when V_CC drops to GND)	See Figure 10-1	0.001		ms
V_{CC_TRR_POR50}	Time to re-ramp (when V_CC drops to V_{POR_MIN} – 50 mV)	See Figure 10-2	0.001		ms
V_{CC_GH}	Level that V_CCP can glitch down to, but not cause a functional disruption when V_{CCX_GW} = 1 μs	See Figure 10-3		1.2	V
V_{CC_GW}	Glitch width that will not cause a functional disruption when V_{CCX_GH} = 0.5 × V_CCx	See Figure 10-3			μs
V_PORF	Voltage trip point of POR on falling V_CC		0.767	1.144	V
V_PORR	Voltage trip point of POR on rising V_CC		1.033	1.428	V

(1) T_A = –40°C to 85°C (unless otherwise noted)

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and the device impedance are factors that affect power-on reset performance. Figure 10-3 and Table 10-1 provide more information on how to measure these specifications.

Figure 10-3 Glitch Width And Glitch Height

V_POR is critical to the power-on reset. V_POR is the voltage level at which the reset condition is released and all the registers and the I²C/SMBus state machine are initialized to their default states. The value of V_POR differs based on the V_CC being lowered to or from 0. Figure 10-4 and Table 10-1 provide more details on this specification.

Figure 10-4 V_POR