米6体育平台手机版

ZHCSJK4G June 2009 – March 2021 PCA9548A

PRODUCTION DATA

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机械数据 (封装 | 引脚)

DGV|24
- MPDS006C
PW|24
- MPDS363A
RGE|24
- MPQF124G
DW|24
- MPDS174A
DB|24
- MPDS509

散热焊盘机械数据 (封装 | 引脚)

RGE|24
- QFND024AD

订购信息

6.6 I²C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)

			MIN	MAX	UNIT
STANDARD MODE
f_scl	I²C clock frequency		0	100	kHz
t_sch	I²C clock high time		4		μs
t_scl	I²C clock low time		4.7		μs
t_sp	I²C spike time			50	ns
t_sds	I²C serial-data setup time		250		ns
t_sdh	I²C serial-data hold time		0⁽¹⁾		μs
t_icr	I²C input rise time			1000	ns
t_icf	I²C input fall time			300	ns
t_ocf	I²C output (SDn) fall time (10-pF to 400-pF bus)			300	ns
t_buf	I²C bus free time between stop and start		4.7		μs
t_sts	I²C start or repeated start condition setup		4.7		μs
t_sth	I²C start or repeated start condition hold		4		μs
t_sps	I²C stop condition setup		4		μs
t_vdL(Data)	Valid-data time (high to low)⁽³⁾	SCL low to SDA output low valid		1	μs
t_vdH(Data)	Valid-data time (low to high)⁽³⁾	SCL low to SDA output high valid		0.6	μs
t_vd(ack)	Valid-data time of ACK condition	ACK signal from SCL low to SDA output low		1	μs
C_b	I²C bus capacitive load			400	pF
FAST MODE
f_scl	I²C clock frequency		0	400	kHz
t_sch	I²C clock high time		0.6		μs
t_scl	I²C clock low time		1.3		μs
t_sp	I²C spike time			50	ns
t_sds	I²C serial-data setup time		100		ns
t_sdh	I²C serial-data hold time		0⁽¹⁾		μs
t_icr	I²C input rise time		20 + 0.1C_b ⁽²⁾	300	ns
t_icf	I²C input fall time		20 + 0.1C_b ⁽²⁾	300	ns
t_ocf	I²C output (SDn) fall time (10-pF to 400-pF bus)		20 + 0.1C_b ⁽²⁾	300	ns
t_buf	I²C bus free time between stop and start		1.3		μs
t_sts	I²C start or repeated start condition setup		0.6		μs
t_sth	I²C start or repeated start condition hold		0.6		μs
t_sps	I²C stop condition setup		0.6		μs
t_vdL(Data)	Valid-data time (high to low)⁽³⁾	SCL low to SDA output low valid		1	μs
t_vdH(Data)	Valid-data time (low to high)⁽³⁾	SCL low to SDA output high valid		0.6	μs
t_vd(ack)	Valid-data time of ACK condition	ACK signal from SCL low to SDA output low		1	μs
C_b	I²C bus capacitive load			400	pF

(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the V_IH min of the SCL signal), to bridge the undefined region of the falling edge of SCL.

(2) C_b = total bus capacitance of one bus line in pF.

(3) Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 7-2).

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机械数据 (封装 | 引脚)

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.6 I2C Interface Timing Requirements

6.6 I²C Interface Timing Requirements