ZHCSHU7J August   2005  – March 2021 PCA9555

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Features
      1. 8.3.1 Power-On Reset (POR)
      2. 8.3.2 I/O Port
    4. 8.4 Device Functional Modes
      1. 8.4.1 Interrupt ( INT) Output
        1. 8.4.1.1 Interrupt Errata
          1. 8.4.1.1.1 INT Description
          2. 8.4.1.1.2 System Impact
          3. 8.4.1.1.3 System Workaround
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 Register Map
        1. 8.5.2.1 Device Address
        2. 8.5.2.2 Control Register And Command Byte
        3. 8.5.2.3 Register Descriptions
        4. 8.5.2.4 Bus Transactions
          1. 8.5.2.4.1 Writes
          2. 8.5.2.4.2 Reads
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. 9.1.1.1 Design Requirements
        2. 9.1.1.2 Design Requirements
          1. 9.1.1.2.1 Minimizing ICC When I/O Is Used To Control Led
        3. 9.1.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

Figure 5-1 DB, DBQ, DGV, DW or PW Package, 24 Pin (SOP), (Top View)
Figure 5-2 RGE Package, 24 Pin (QFN), (Top View)
Table 5-1 Pin Functions
PIN DESCRIPTION
NAME SSOP (DB),
QSOP (DBQ),
TSSOP (PW), AND
TVSOP (DGV)		 QFN (RGE)
INT 1 22 Interrupt output. Connect to VCC through a pullup resistor.
A1 2 23 Address input 1. Connect directly to VCC or ground.
A2 3 24 Address input 2. Connect directly to VCC or ground.
P00 4 1 P-port input/output. Push-pull design structure.
P01 5 2 P-port input/output. Push-pull design structure.
P02 6 3 P-port input/output. Push-pull design structure.
P03 7 4 P-port input/output. Push-pull design structure.
P04 8 5 P-port input/output. Push-pull design structure.
P05 9 6 P-port input/output. Push-pull design structure.
P06 10 7 P-port input/output. Push-pull design structure.
P07 11 8 P-port input/output. Push-pull design structure.
GND 12 9 Ground
P10 13 10 P-port input/output. Push-pull design structure.
P11 14 11 P-port input/output. Push-pull design structure.
P12 15 12 P-port input/output. Push-pull design structure.
P13 16 13 P-port input/output. Push-pull design structure.
P14 17 14 P-port input/output. Push-pull design structure.
P15 18 15 P-port input/output. Push-pull design structure.
P16 19 16 P-port input/output. Push-pull design structure.
P17 20 17 P-port input/output. Push-pull design structure.
A0 21 18 Address input 0. Connect directly to VCC or ground.
SCL 22 19 Serial clock bus. Connect to VCC through a pullup resistor.
SDA 23 20 Serial data bus. Connect to VCC through a pullup resistor.
VCC 24 21 Supply voltage
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