ZHCSHU7J August 2005 – March 2021 PCA9555
PRODUCTION DATA
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
I2C BUS—STANDARD MODE | |||||
fscl | I2C clock frequency | 0 | 100 | kHz | |
tsch | I2C clock high time | 4 | µs | ||
tscl | I2C clock low time | 4.7 | µs | ||
tsp | I2C spike time | 50 | ns | ||
tsds | I2C serial-data setup time | 250 | ns | ||
tsdh | I2C serial-data hold time | 0 | ns | ||
ticr | I2C input rise time | 1000 | ns | ||
ticf | I2C input fall time | 300 | ns | ||
tocf | I2C output fall time | 10-pF to 400-pF bus | 300 | ns | |
tbuf | I2C bus free time between stop and start | 4.7 | µs | ||
tsts | I2C start or repeated start condition setup | 4.7 | µs | ||
tsth | I2C start or repeated start condition hold | 4 | µs | ||
tsps | I2C stop condition setup | 4 | µs | ||
tvd(data) | Valid data time | SCL low to SDA output valid | 3.45 | µs | |
tvd(ack) | Valid data time of ACK condition | ACK signal from SCL low to SDA (out) low | 3.45 | µs | |
Cb(1) | I2C bus capacitive load | 400 | pF | ||
I2C BUS—FAST MODE | |||||
fscl | I2C clock frequency | 0 | 400 | kHz | |
tsch | I2C clock high time | 0.6 | µs | ||
tscl | I2C clock low time | 1.3 | µs | ||
tsp | I2C spike time | 50 | ns | ||
tsds | I2C serial-data setup time | 100 | ns | ||
tsdh | I2C serial-data hold time | 0 | ns | ||
ticr | I2C input rise time | 20 | 300 | ns | |
ticf | I2C input fall time | 20 × (VCC / 5.5 V) | 300 | ns | |
tocf | I2C output fall time | 10-pF to 400-pF bus | 20 × (VCC / 5.5 V) | 300 | ns |
tbuf | I2C bus free time between stop and start | 1.3 | µs | ||
tsts | I2C start or repeated start condition setup | 0.6 | µs | ||
tsth | I2C start or repeated start condition hold | 0.6 | µs | ||
tsps | I2C stop condition setup | 0.6 | µs | ||
tvd(data) | Valid data time | SCL low to SDA output valid | 0.9 | µs | |
tvd(ack) | Valid data time of ACK condition | ACK signal from SCL low to SDA (out) low | 0.9 | µs | |
Cb(1) | I2C bus capacitive load | 400 | pF |