米6体育平台手机版

ZHCSX36K July 2001 – September 2024 PCF8574

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

PW|20
- MPDS362A
N|16
- MPDI002C
RGY|20
- MPQF116H
DW|16
- MSOI003I
DGV|20
- MPDS006C
RGT|16
- MPQF119H

散热焊盘机械数据 (封装 | 引脚)

RGY|20
- QFND041R
DW|16
- QFND313D
RGT|16
- QFND097Q

订购信息

zhcsx36k_oa

8.3.1 Power-On Reset Requirements

In the event of a glitch or data corruption, the PCF8574 device can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 8-6 and Figure 8-7.

PCF8574 VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC

Figure 8-6 V_CC is Lowered Below 0.2 V or 0 V and Then Ramped Up to V_CC

PCF8574 VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC

Figure 8-7 V_CC is Lowered Below the POR Threshold, Then Ramped Back Up to V_CC

Table 8-1 specifies the performance of the power-on reset feature for PCF8574 for both types of power-on reset.

Table 8-1 Recommended Supply Sequencing and Ramp Rates⁽¹⁾

PARAMETER			MIN	MAX	UNIT
V_{CC_FT}	Fall rate	See Figure 8-6	1	100	ms
V_{CC_RT}	Rise rate	See Figure 8-6	0.01	100	ms
V_{CC_TRR_GND}	Time to re-ramp (when V_CC drops to GND)	See Figure 8-6	0.001		ms
V_{CC_TRR_POR50}	Time to re-ramp (when V_CC drops to V_{POR_MIN} – 50 mV)	See Figure 8-7	0.001		ms
V_{CC_GH}	Level that V_CCP can glitch down to, but not cause a functional disruption when V_{CCX_GW} = 1 μs	See Figure 8-8		1.2	V
V_{CC_GW}	Glitch width that will not cause a functional disruption when V_{CCX_GH} = 0.5 × V_CCx	See Figure 8-8			μs
V_PORF	Voltage trip point of POR on falling V_CC		0.99	1.28	V
V_PORR	Voltage trip point of POR on fising V_CC		1.190	1.410	V

(1) T_A = –40°C to 85°C (unless otherwise noted)

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 8-8 and Table 8-1 provide more information on how to measure these specifications.

Figure 8-8 Glitch Width and Glitch Height

V_POR is critical to the power-on reset. V_POR is the voltage level at which the reset condition is released and all the registers and the I²C/SMBus state machine are initialized to their default states. The value of V_POR differs based on the V_CC being lowered to or from 0. Figure 8-9 and Table 8-1 provide more details on this specification.

Figure 8-9 V_POR