SBAS448B October   2008  – August 2015 PCM1690

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Digital Input/Output
    6. 6.6  Electrical Characteristics: DAC
    7. 6.7  Electrical Characteristics: Power-Supply Requirements
    8. 6.8  System Clock Timing Requirements
    9. 6.9  Audio Interface Timing Requirements for Left-Justified, Right-Justified, and I2S Data Formats
    10. 6.10 Audio Interface Timing Requirements for DSP and TDM Data Formats
    11. 6.11 Three-Wire Serial Control Interface Timing Requirements
    12. 6.12 SCL and SDA Control Interface Timing Requirements
    13. 6.13 Typical Characteristics
      1. 6.13.1 Digital Filter
      2. 6.13.2 Digital De-Emphasis Filter
      3. 6.13.3 Dynamic Performance
      4. 6.13.4 Output Spectrum
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Outputs
      2. 7.3.2  Voltage Reference VCOM
      3. 7.3.3  System Clock Input
      4. 7.3.4  Sampling Mode
      5. 7.3.5  Reset Operation
      6. 7.3.6  Zero Flag
      7. 7.3.7  AMUTE Control
      8. 7.3.8  Three-Wire (SPI) Serial Control
      9. 7.3.9  Control Data Word Format
      10. 7.3.10 Register Write Operation
      11. 7.3.11 Two-Wire (I2C) Serial Control
      12. 7.3.12 Packet Protocol
      13. 7.3.13 Write Operation
      14. 7.3.14 Read Operation
      15. 7.3.15 Timing Requirements: SCL and SDA
    4. 7.4 Device Functional Modes
      1. 7.4.1 Audio Serial Port Operation
      2. 7.4.2 Audio Data Interface Formats and Timing
      3. 7.4.3 Synchronization With the Digital Audio System
      4. 7.4.4 Mode Control
      5. 7.4.5 Parallel Hardware Control
    5. 7.5 Register Maps
      1. 7.5.1 Control Register Definitions (Software Mode Only)
      2. 7.5.2 Register Definitions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Lowpass Filter and Differential-to-Single-Ended Converter for DAC Outputs
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Hardware Control Method
        2. 8.2.2.2 Audio Input
        3. 8.2.2.3 Audio Output
        4. 8.2.2.4 Master Clock
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Lowpass Filter and Differential-to-Single-Ended Converter for DAC Outputs

ΔΣ DACs use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR) performance at the expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2. The out-of-band noise must be lowpass filtered in order to provide optimal converter performance. This filtering is accomplished by a combination of on-chip and external lowpass filters.

Figure 39 and Figure 40 show the recommended external differential-to-single-ended converter with lowpass active filter circuits for AC-coupled and DC-coupled applications. These circuits are second-order Butterworth filters using a multiple feedback (MFB) circuit arrangement that reduces sensitivity to passive component variations over frequency and temperature. For more information regarding MFB active filter designs, please refer to Applications Bulletin SBAA055, Dynamic Performance Testing of Digital Audio D/A Converters, available from the TI web site (www.ti.com) or the local Texas Instruments' sales office.

Because the overall system performance is defined by the quality of the DACs and the associated analog output circuitry, high-quality audio op amps are recommended for the active filters. Texas Instruments’ OPA2134, OPA2353, and NE5532A dual op amps are shown in Figure 39 and Figure 40, and are recommended for use with the PCM1690.

PCM1690 ai_post_lpf_ac_bas448.gif
NOTE: Amplifier is an NE5532A x1/2 or OPA2134 x1/2; R1 = 7.5-kΩ; R2 = 5.6-kΩ; R3 = 360-Ω; C1 = 3300-pF; C2 = 680-pF; Gain = 0.747; f–3 dB = 53 kHz.
Figure 39. AC-Coupled, Post-LPF and Differential to Single-Ended Buffer
PCM1690 ai_post_lpf_dc_bas448.gif
NOTE: Amplifier is an NE5532A x1/2 or OPA2134 x1/2; R1 = 15-kΩ; R2 = 11-kΩ; R3 = 820-Ω; C1 = 1500-pF; C2 = 330-pF; Gain = 0.733; f–3 dB = 54 kHz.
Figure 40. DC-Coupled, Post-LPF and Differential to Single-Ended Buffer

8.2 Typical Application

A basic connection diagram is shown in Figure 41, with the necessary power-supply bypassing and decoupling components. Texas Instruments’ PLL170X is used to generate the system clock input at SCKI, as well as to generate the clock for the audio signal processor. The use of series resistors (22 Ω to 100 Ω) are recommended for SCKI, LRCK, BCK, DIN1, DIN2, DIN3, and DIN4 for electromagnetic interference (EMI) reduction.

PCM1690 ai_basic_bas448.gif
NOTE: C1 through C3 are 1-μF ceramic capacitors. C4 through C6 are 10-μF electrolytic capacitors. R1 through R7 are 22-Ω to 100-Ω resistors. R8 and R9 are resistors appropriate for pull-up. R10 is less than 10 kΩ.
Figure 41. Basic Connection Diagram

8.2.1 Design Requirements

  • Control: Hardware, I2C, or SPI
  • Audio Input: PCM Serial data, TDM, or DSP
  • Audio Output: (1.6 × VCC1) Vpp analog audio biased to (0.5 × VCC1) V
  • Master Clock: PLL170X IC

8.2.2 Detailed Design Procedure

8.2.2.1 Hardware Control Method

There are 3 ways to control the PCM1690, hardware control, SPI, or I2C. Hardware control will provide a limited access to control features available in the PCM1690 but can be implemented with pull up and pull downs, or with GPIO of a microcontroller. Control via SPI or I2C will provide access to all control registers and features but will require a digital device that can implement SPI or I2C.

8.2.2.2 Audio Input

For Audio Input there are 3 options, PCM serial data, TDM, or DSP. All three will support the same quality of audio data, but having these 3 options to match the audio sources available outputs allows for greater flexibility. This selection is made by configuring the MODE pin which is detailed in Table 6 and shown in Pin Functions.

8.2.2.3 Audio Output

The output of the PCM1690 will produce a differential (1.6 × VCC1) Vpp signal at full scale into a 5-kΩ load, that must be filtered before being sent to an amplifier. Outputs Vout1 through Vout 8 will be biased at (0.5 × VCC1) V.

8.2.2.4 Master Clock

The master clock can come from wither a dedicated IC such as the PLL170X series, a crystal or the audio source IC. What is important is that the audio source and the PCM1690 are driven from the same source so that the audio clocks will be synchronous.

8.2.3 Application Curve

PCM1690 tc_fresp_single_bas448.gifFigure 42. Frequency Response
(Single Rate)
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