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ZHCSK28E April 2003 – July 2019 PCM1753 , PCM1754 , PCM1755

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8.3.1.1 System Clock Input

The PCM175x devices require a system clock for operating the digital interpolation filters and multilevel delta-sigma modulators. The system clock is applied at the SCK input (pin 16). Table 1 lists examples of system clock frequencies for common audio sampling rates.

Figure 20 shows and the System Clock Input Timing table lists he timing requirements for the system clock input. For optimal performance, use a clock source with low phase-jitter and noise. TI's PLL170x family of multiclock generators is an excellent choice for providing the PCM175x system clock.

Table 1. System Clock Rates for Common Audio Sampling Frequencies

SAMPLING FREQUENCY	SYSTEM CLOCK FREQUENCY (f_SCLK) (MHz)
SAMPLING FREQUENCY	128 f_S	192 f_S	256 f_S	384 f_S	512 f_S	768 f_S	1152 f_S
8 kHz	1.024	1.536	2.048	3.072	4.096	6.144	9.216
16 kHz	2.048	3.072	4.096	6.144	8.192	12.288	18.432
32 kHz	4.096	6.144	8.192	12.288	16.384	24.576	36.864
44.1 kHz	5.6448	8.4672	11.2896	16.9344	22.5792	33.8688	⁽¹⁾
48 kHz	6.144	9.216	12.288	18.432	24.576	36.864	⁽¹⁾
88.2 kHz	11.2896	16.9344	22.5792	33.8688	45.1584	⁽¹⁾	⁽¹⁾
96 kHz	12.288	18.432	24.576	36.864	49.152	⁽¹⁾	⁽¹⁾
192 kHz	24.576	36.864	⁽¹⁾	⁽¹⁾	⁽¹⁾	⁽¹⁾	⁽¹⁾

(1) This system clock rate is not supported for the given sampling frequency.

PCM1753 PCM1754 PCM1755 sys_clock_input_timing_les254.gif

Figure 20. System Clock Input Timing