ZHCSK28E April 2003 – July 2019 PCM1753 , PCM1754 , PCM1755
PRODUCTION DATA.
If a zero-detect condition exists for one or more channels, the zero flag pins for those channels are set to a logic 1 state. There are zero flag pins for each channel, ZEROL (pin 12) and ZEROR (pin 11). These pins can be used to operate external mute circuits, or used as status indicators for a microcontroller, audio signal processor, or other digitally controlled function. The active polarity of zero flag outputs can be inverted by setting the ZREV bit of control register 22 to 1. The reset default is active-high output, or ZREV = 0. The L-channel and R-channel common zero flag can be selected by setting the AZRO bit of control register 22 to 1. The reset default is independent zero flags for L-channel and R-channel, or AZRO = 0.