9.1 Application Information

The delta-sigma section of the PCM175x device is based on an 8-level amplitude quantizer and a 4th-order noise shaper. This section converts the oversampled input data to 8-level delta-sigma format. A block diagram of the 8-level delta-sigma modulator is shown in Figure 32. This 8-level delta-sigma modulator has the advantage of stability and clock jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator.

The combined oversampling rate of the delta-sigma modulator and the interpolation filter is 64 f_S.

The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown in Figure 35 and Figure 36. The enhanced multilevel delta-sigma architecture also has advantages for input clock jitter sensitivity due to the multilevel quantizer, with the simulated jitter sensitivity shown in Figure 37.

The PCM175X devices are suitable for a wide variety of cost-sensitive consumer applications requiring good performance and operation with a single 5-V supply.