10.1 Layout Guidelines

Designers should try to use the same ground between AGND and DGND to avoid any potential voltage difference between them. Ensure that the return currents for digital signals will avoid the AGND pin or the input signals to the I/V stage. Avoid running high-frequency clock and control signals near AGND, or any of the VOUT pins where possible. The pin layout of the PCM1795 device partitions into two sides, the analog side and the digital side. Providing the system is partitioned in such a way that digital signals are routed away from the analog sections, then no digital return currents (for example, clocks) should be generated in the analog circuitry.

• Decoupling capacitors should be placed as close to the V_CC1, V_CC2L, V_CCR2, V_COML, V_COMR, and V_DD pins as possible.
• Further guidelines can be found in Figure 83.

10.2 Layout Example

Figure 83. Layout Recommendation