ZHCSMZ3A December   2020  – June 2021 PCM1820 , PCM1821

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 7.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Audio Serial Interfaces
        1. 8.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 8.3.2.2 Inter IC Sound (I2S) Interface
      3. 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 8.3.4 Input Channel Configurations
      5. 8.3.5 Reference Voltage
      6. 8.3.6 Signal-Chain Processing
        1. 8.3.6.1 Digital High-Pass Filter
        2. 8.3.6.2 Configurable Digital Decimation Filters
          1. 8.3.6.2.1 Linear Phase Filters
            1. 8.3.6.2.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.6.2.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.6.2.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.6.2.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.6.2.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.6.2.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.6.2.1.7 Sampling Rate: 192 kHz or 176.4 kHz
          2. 8.3.6.2.2 Low-Latency Filters
            1. 8.3.6.2.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.2.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.2.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.2.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.2.2.5 Sampling Rate: 96 kHz or 88.2 kHz
      7. 8.3.7 Dynamic Range Enhancer (DRE)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.4.1 Active Mode

The device wakes up in active mode when AVDD and IOVDD are available. Configure all hardware control pins (MSZ, MD0, MD1, and FMT0) for the device desired mode of operation before enabling clocks for the device.

In active mode, when the audio clocks are available, the device automatically powers up all ADC channels and starts transmitting data over the audio serial interface. If the clocks are stopped, then the device auto powers down the ADC channels.
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