9.3.1 Clock and Reset

For both USB and audio functions, the PCM2704C/5C/6C/7C require a 12-MHz (±500 ppm) clock that can be generated by the onboard oscillator using a 12-MHz crystal resonator. The 12-MHz crystal resonator must be connected to the XTI pin (pin 28 for the PCM2704C/5C, pin 12 for the PCM2706C/7C) and the XTO pin (pin 1 for the PCM2704C/5C, pin 13 for the PCM2706C/7C) with one large (1-MΩ) resistor and two small capacitors; the capacitance of these components depends on the specified load capacitance of the crystal resonator. An external clock can be supplied from XTI (pin 28 for the PCM2704C/5C, pin 12 for the PCM2706C/7C). If an external clock is supplied, XTO (pin 1 for the PCM2704C/5C, pin 13 for the PCM2706C/7C) must be left open. No clock disabling pin is provided; therefore, TI does not recommend to use the external clock supply. SSPND (pin 27 for the PCM2704C/5C, pin 11 for the PCM2706C/7C) cannot use clock disabling.

The PCM2704C/5C/6C/7C have an internal power-on reset circuit, which works automatically when V_DD (pin 7 for the PCM2704C/5C, pin 21 for the PCM2706C/7C) exceeds 2-V typical (1.6 to 2.4 V), which is equivalent to V_BUS (pin 10 for the PCM2704C/5C, pin 24 for the PCM2706C/7C) exceeding 3-V typical for bus-powered applications. Approximately 700 μs is required until an internal reset release occurs.

9.3.2 Operation Mode Selection

The PCM2704C/5C/6C/7C have the following mode-select pins.

9.3.3 DAC

The PCM2704C/5C/6C/7C have a DAC that uses an oversampling technique with 128-ƒ_S, second-order, multi-bit noise shaping. This technique provides extremely-low quantization noise in the audio band, and the built-in analog low-pass filter removes the high-frequency components of the noise-shaping signal. The DAC analog outputs, V_OUTL and V_OUTR , are sent through the headphone amplifier and can provide 12 mW at 32 Ω as well as 1.8 V_PP into a 10-kΩ load.

9.3.4 Digital Audio Interface: S/PDIF Output

The PCM2704C/5C/6C/7C employ S/PDIF output. Isochronous-out data from the host are encoded to S/PDIF output DOUT, as well as to DAC analog outputs V_OUTL and V_OUTR. The interface format and timing follow the IEC-60958 standard. Monaural data are converted to the stereo format at the same data rate. S/PDIF output is not supported in the I²S I/F enable mode. The implementation of this feature is optional.

9.3.5 Digital Audio Interface: I²S Interface Output (PCM2706C/7C)

The PCM2706C and PCM2707C can support the I²S interface, which is enabled by the FSEL pin (pin 9). In the I²S interface-enabled mode, pins 4, 18, 19, 5, and 17 are assigned as DIN, SYSCK, BCK, LRCK, and DOUT, respectively. These pins provide digital output/input data in the 16-bit I²S format, which is also accepted by the internal DAC. Figure 1, Figure 2, and Figure 3 show the I²S interface format and timing. Audio Interface Timing Characteristics and Audio Clock Timing Characteristics list the audio interface timing and audio clock timing characteristics, respectively.

9.3.6 Descriptor Data Modification

The descriptor data can be modified through the I²C port by external ROM (PCM2704C/6C) or through the SPI port by an SPI host such as an MCU (PCM2705C/7C) under a particular configuration of the PSEL and HOST pins. Setting both the PSEL and the HOST pins high is necessary to modify the descriptor data; the D+ pin pullup resistor must not be activated before programming the descriptor data through the external ROM or SPI port is completed. The descriptor data must be sent from an external ROM to the PCM2704C/6C or from the SPI host to the PCM2705C/7C in LSB first format, with a specified byte order. Additionally, the power attribute and max power contents must be consistent with the PSEL setting and the power usage from the USB V_BUS of the end application. Therefore, the device does not support descriptor data modification in self-powered configuration (PSEL = low).

9.3.7 External ROM Descriptor (PCM2704C/6C)

The PCM2704C/6C support an external ROM interface to override internal descriptors. Pin 3 (for the PCM2704C) or pin 15 (for the PCM2706C) is assigned as DT (serial data), and pin 2 (for the PCM2704C) or pin 14 (for the PCM2706C) is assigned as CK (serial clock) of the I²C interface when using the external ROM descriptor. Descriptor data are transferred from the external ROM to the PCM2704C/6C through the I²C interface the first time when the device is activated after a power-on reset. Before completing a read of the external ROM, the PCM2704C/6C reply with NACK for any USB command request from the host to the device itself. The descriptor data, which can be in the external ROM, must meet these parameters:

• String descriptors must be described in ANSI ASCII code (1 byte for each character).
• String descriptors are converted automatically to unicode strings for transmission to the host.
• The device address of the external ROM is fixed as 0xA0.

The data bits must be sent from LSB to MSB on the I²C bus. This condition means that each byte of data must be stored with its bits in reverse order. A read operation is performed at a frequency of XTI/384 (approximately 30 kHz). The power attribute and max power contents must be consistent with the end application circuit configuration (the PSEL setting and the actual power usage from V_BUS of the USB connector); otherwise, it may cause improper or unexpected PCM2704C/6C operation.

The data must be stored from address 0x00 and must consist of 57 bytes, according to these listed parameters:

• Vendor ID (2 bytes)
• Product ID (2 bytes)
• Product string (16 bytes in ANSI ASCII code)
• Vendor string (32 bytes in ANSI ASCII code)
• Power attribute (1 byte)
• Max power (1 byte)
• Auxiliary HID usage ID in report descriptor (3 bytes)

Figure 28 shows the timing for an external ROM read operation. Table 3 summarizes the timing characteristics.

Figure 28. External ROM Read Operation

9.3.8 External ROM Example

External ROM data (sample set)

Explanation

Data are stored beginning at address 0x00

Vendor ID: 0x08BB

Product ID: 0x2704

Product string: Product strings (16 bytes)

Vendor string: Vendor strings are placed here (32 bytes, 31 visible characters are followed by 1 space).

Power attribute (bmAttribute): 0x80 (bus-powered)

Max power (maxPower): 0x7D (250 mA)

Auxiliary HID usage ID: 0x0A, 0x93, 0x01 (AL A/V capture)

Note that the data bits must be sent from LSB to MSB on the I²C bus. Therefore, each data byte must be stored with its bits in reverse order.

9.3.9 Serial Programming Interface (PCM2705C/7C)

The PCM2705C/7C supports a SPI to program the descriptor and to set the HID state. External ROM Descriptor (PCM2704C/6C) describes descriptor data. Figure 5 shows the SPI timing; SPI Timing Characteristics lists the respective timing characteristics.

Figure 29 shows the SPI write timing sequence.

Figure 29. SPI Write Operation

9.3.10 USB Host Interface Sequence

9.3.10.1 Power-On, Attach, and Playback Sequence

The PCM2704C/5C/6C/7C are ready for setup when the reset sequence has finished and the USB bus is attached. After a connection has been established (through the setup process), the PCM2704C/5C/6C/7C are ready to accept USB audio data. While waiting for the audio data (that is, the device is in an idle state), the analog output is set to bipolar zero (BPZ).

Upon receiving the audio data, the PCM2704C/5C/6C/7C stores the first audio packet in the internal storage buffer. The packet contains 1 ms of audio data. The PCM2704C/5C/6C/7C start playing the audio data after detecting the next subsequent start-of-frame (SOF) packet. Figure 30 shows the initial operation sequence for the device.

Figure 30. Initial Sequence

9.3.10.2 Play, Stop, and Detach Sequence

When the host finishes or aborts playback, the PCM2704C/5C/6C/7C stop playing after the last audio data output is complete. Figure 31 shows the play, stop, and detach sequence.

Figure 31. Play, Stop, and Detach Sequence

9.3.10.3 Suspend and Resume Sequence

The PCM2704C/5C/6C/7C enter a suspended state after the USB bus has been in a constant idle state for approximately 5 ms. While the PCM2704C/5C/6C/7C are in this suspended state, the SSPND flag (pin 27 for the PCM2704C/5C, pin 11 for the PCM2706C/7C) is asserted. The PCM2704C/5C/6C/7C wake up immediately when detecting a non-idle state on the USB bus. Figure 32 shows the operating sequence for the suspend and resume process.

Figure 32. Suspend and Resume

9.3.11 Operating Environment

For current information on the PCM2704C/2705C/2706C/2707C operating environments, see the Updated Operating Environments for PCM270X, PCM290X Applications application report, SLAA374, available through the TI website at www.ti.com.

9.5.1 USB Interface

Control data and audio data are transferred to the PCM2704C/5C/6C/7C through the D+ pin (pin 9 for the PCM2704C/5C, pin 23 for the PCM2706C/7C) and D– pin (pin 8 for the PCM2704C/5C, pin 22 for the PCM2706C/7C). D+ should be pulled up with a 1.5-kΩ (±5%) resistor. To avoid back voltage in self-powered operation, the device must not provide power to the pullup resistor on D+ while V_BUS of the USB port is inactive.

All data to/from the PCM2704C/5C/6C/7C are transferred at full speed. Table 4 shows the information that is provided in the device descriptor. Some parts of the device descriptor can be modified through external ROM (PCM2704C/6C) or SPI (PCM2705C/7C).

Table 5 shows the information contained in the configuration descriptor. Some parts of the configuration descriptor can be modified through external ROM (PCM2704C/6C) or SPI (PCM2705C/7C).

Table 6 shows the information contained in the string descriptor. Some parts of the string descriptor can be modified through external ROM (PCM2704C/6C) or SPI (PCM2705C/7C).

9.5.1.1 Device Configuration

Figure 33 shows the USB audio function topology. The PCM2704C/5C/6C/7C have three interfaces. Each interface is enabled by different alternative settings.

Figure 33. USB Audio Function Topology

9.6.1 SPI Register (PCM2705C/7C)