The standard I²S protocol is defined for only two channels: left and right. The device extends the same protocol timing for multichannel operation. In I²S mode, the MSB of the left slot 0 is transmitted on the falling edge of BCLK in the second cycle after the falling edge of FSYNC. Immediately after the left slot 0 data transmission, the remaining left slot data are transmitted in order. The MSB of the right slot 0 is transmitted on the falling edge of BCLK in the second cycle after the rising edge of FSYNC. Immediately after the right slot 0 data transmission, the remaining right slot data are transmitted in order. FSYNC and each data bit is transmitted on the falling edge of BCLK. Figure 8-5 to Figure 8-8 illustrate the protocol timing for I²S operation with various configurations.

Figure 8-5 I²S Mode Standard Protocol Timing (TX_OFFSET = 0)

Figure 8-6 I²S Protocol Timing (TX_OFFSET = 1)

Figure 8-7 I²S Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)

Figure 8-8 I²S Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)

For proper operation of the audio bus in I²S mode, the number of bit clocks per frame must be greater than or equal to the number of active output channels (including left and right slots) times the programmed word length of the output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC high pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots times the data word length configured.