at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load
on all outputs (unless otherwise noted); see Figure 7-2 for timing diagram
|
MIN |
NOM |
MAX |
UNIT |
| t(BCLK) |
BCLK period |
40 |
|
|
ns |
| tH(BCLK) |
BCLK high pulse duration (1) |
25 |
|
|
ns |
| tL(BCLK) |
BCLK low pulse duration (1) |
25 |
|
|
ns |
| tSU(FSYNC) |
FSYNC setup time |
8 |
|
|
ns |
| tHLD(FSYNC) |
FSYNC hold time |
8 |
|
|
ns |
| tr(BCLK) |
BCLK rise time |
10% - 90% rise time(2) |
|
|
10 |
ns |
| tf(BCLK) |
BCLK fall time |
90% - 10% fall time(2) |
|
|
10 |
ns |
(1) The BCLK minimum high or low pulse duration can be relaxed to 14 ns (to meet the timing specifications), if the SDOUT data line is latched on the same BCLK edge polarity as the edge used by the device to transmit SDOUT data.
(2) The BCLK maximum rise and fall time can be relaxed to 13 ns if the BCLK frequency used in the system is below 20 MHz. Relaxing the BCLK rise and fall time can cause noise to increase because of higher clock jitter.