ZHCSA60C May   2012  – May 2015 PCM5100A , PCM5100A-Q1 , PCM5101A , PCM5101A-Q1 , PCM5102A , PCM5102A-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 简化系统图
  5. 5 修订历史记录
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings Updated ESD Data
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Timing Requirements, XSMT
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Terminology
      2. 9.3.2 Audio Data Interface
        1. 9.3.2.1 Audio Serial Interface
        2. 9.3.2.2 PCM Audio Data Formats
        3. 9.3.2.3 Zero Data Detect
      3. 9.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
      4. 9.3.4 Audio Processing
        1. 9.3.4.1 Interpolation Filter
      5. 9.3.5 Reset and System Clock Functions
        1. 9.3.5.1 Clocking Overview
        2. 9.3.5.2 Clock Slave Mode With Master/System Clock (SCK) Input (4 Wire I2S)
        3. 9.3.5.3 Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM)
    4. 9.4 Device Functional Modes
      1. 9.4.1 External SCK and PLL Activation
        1. 9.4.1.1 Interpolation Filter Modes
        2. 9.4.1.2 44.1kHz De-emphasis
        3. 9.4.1.3 Audio Format
  10. 10Applications and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Typical Applications
        1. 10.1.1.1 Example Design Requirements
        2. 10.1.1.2 Detailed Design Procedure
        3. 10.1.1.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Distribution and Requirements
    2. 11.2 Recommended Powerdown Sequence
      1. 11.2.1 Planned Shutdown
      2. 11.2.2 Unplanned Shutdown
    3. 11.3 External Power Sense Undervoltage Protection Mode
    4. 11.4 Power-On Reset Function
    5. 11.5 PCM510xA Power Modes
      1. 11.5.1 Setting Digital Power Supplies and I/O Voltage Rails
      2. 11.5.2 Power Save Modes
  12. 12Layout
    1. 12.1 Layout Guidelines
  13. 13器件和文档支持
    1. 13.1 相关链接
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
  14. 14机械、封装和可订购信息
    1. 14.1 机械数据

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 修订历史记录

Changes from B Revision (January 2015) to C Revision

  • Changed 简化系统图Go
  • Changed typical performance table to reflect part differences accurately Go
  • Changed "Storage temperatures, Tstg" to "Operating junction temperature range at –40°C to 130°C"Go
  • Changed "Storage temperature (Q1 devices) –40°C to 125°C" to "Storage temperatures, Tstg –65°C to 150°C"Go
  • Updated ESD Data Go
  • Changed the stereo line output load resistance MIN value in the Recommended Operating Conditions from "2 kΩ" to "1 kΩ"Go
  • Changed the operating junction temperature range in the Recommended Operating Conditions from "MIN = –25°C MAX = 85°C" to "MIN = –40°C MAX = 130°C"Go
  • Added "Q1 Automotive grade devices..." and "Consumer grade (non-Q1) devices..." to the condition statement in the Electrical CharacteristicsGo
  • Changed "Gain error on Q1 Devices" to "Gain error on Q1 Automotive Grade Devices" in Electrical CharacteristicsGo
  • Changed min/max bipolar offset error for PCM5xx2 to be ±2 mV Go
  • Updated graph titles with device prefixGo
  • Added "Q1 Automotive grade devices..." and "Consumer grade (non-Q1) devices..." to the condition statement in the Typical Characteristics graphs section.Go
  • Changed "MCK" to "SCK" at the PLL Clock in the Functional Block DiagramGo
  • Added details to Zero Data Detection about the default behavior of the device Go
  • Added label "Mute Circuit" and ground symbols to pins DEMP and FMT in Figure 33 Go
  • Added details about fast control of XSMT Go

Changes from A Revision (September 2012) to B Revision

  • Added ESD 额定值表，详细 说明部分，应用和实施部分，电源相关建议部分，器件和文档支持部分以及机械、封装和可订购信息Go
  • Added 1.8V DVDD 电源项Go
  • Changed 特性列表。Go
  • Changed "Operating temperature range " to "Operating junction temperature range"Go
  • Deleted redundant PLL specification in the Recommended Operating Conditions Go
  • Deleted "Intelligent clock error..." and "...for pop-free performance."Go
  • Clarified clock generation explanationGo
  • Clarified external SCK discussion.Go
  • Deleted "The PCM510xA disables the internal PLL when an external SCK is supplied."Go

Changes from * Revision (May 2012) to A Revision

  • Changed 前两页的编排Go
  • Changed "VOUT = –1 dB" to "THD+N at –1 dBFS" in in the Dymamic Performance section of the Electrical CharacteristicsGo
  • Changed reference to correct footnoteGo
  • Changed tSCKH and tSCKL values to 9ns.Go
  • Removed 48kHz sample rate with PLL-generated clockGo
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