ZHCSAC2C August 2012 – October 2018 PCM5121 , PCM5122
PRODUCTION DATA.
The PCM512x supports a wide range of options to generate the required clocks for the DAC section as well as interface and other control blocks as shown in Figure 63.
The clocks for the PLL require a source reference clock. This clock is sourced as the incoming BCK or SCK. In software mode, a GPIO can also be used.
The source reference clock for the PLL reference clock is selected by programming the SRCREF value on Page 0, Register 13, D(6:4). The PCM512x provides several programmable clock dividers to achieve a variety of sampling rates for the DAC and clocks for the NCP, OSR, and the audio processor. OSRCK for OSR must be set at 16 fS frequency by DOSR on Page0, Register 30, D(6:0). See Figure 63.
If PLL functionality is not required, set the PLLEN value on Page 0, Register 4, D(0) to 0. In this situation, an external SCK is required.
| CLOCK MULTIPLEXER | FUNCTION | BITS |
|---|---|---|
| SRCREF | PLL reference | Page 0, Register 13, D(6:4) |
| DIVIDER | FUNCTION | BITS |
| DDSP | audio processor clock divider | Page 0, Register 27, D(6:0) |
| DACCK | DAC clock divider | Page 0, Register 28, D(6:0) |
| CPCK | NCP clock divider | Page 0, Register 29, D(6:0) |
| OSRCK | OSR clock divider | Page 0, Register 30, D(6:0) |
| DBCK | External BCK Div | Page 0, Register 32, D(6:0) |
| DLRK | External LRCK Div | Page 0, Register 33, D(7:0) |