米6体育平台手机版

SLASE12A July 2014 – October 2014 PCM5242

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RHB|32
- MPQF130D

散热焊盘机械数据 (封装 | 引脚)

RHB|32
- QFND029X

订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Supply Voltage	AVDD, CPVDD, DVDD	–0.3	3.9	V
Supply Voltage	LDOO wtih DVDD at 1.8V	–0.3	2.25
Digital Input Voltage	DVDD at 1.8V	–0.3	2.25
Digital Input Voltage	DVDD at 3.3V	–0.3	3.9
Analog Input Voltage		–0.3	3.9

7.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage Temperature		–40	125	°C
V_(ESD)	Electrostatic Discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	–2500	2500	V
V_(ESD)	Electrostatic Discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins	–1500	1500	V

(1) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

				MIN	NOM	MAX	UNIT
AVDD	Analog power supply voltage range	Referenced to AGND⁽¹⁾	VCOM mode	3.0	3.3	3.46	V
AVDD	Analog power supply voltage range	Referenced to AGND⁽¹⁾	VREF mode	3.2	3.3	3.46	V
DVDD	Digital power supply voltage range	Referenced to DGND⁽¹⁾	1.8V DVDD	1.65	1.8	1.95	V
DVDD	Digital power supply voltage range	Referenced to DGND⁽¹⁾	3.3V DVDD	3.1	3.3	3.46	V
CPVDD	Charge pump supply voltage range	Referenced to CPGND⁽¹⁾		3.1	3.3	3.46	V
MCLK	Master Clock Frequency					50	MHz
LOL, LOR	Stereo line output load resistance			2	10		kΩ
C_Lout	Digital output load capacitance				10		pF
T_J	Operating Junction Temperature Range			–25		85	°C

(1) All grounds on board are tied together; they must not differ in voltage by more than 0.2V max, for any combination of ground signals.

7.4 Thermal Information

THERMAL METRIC		RHB (32 PINS)	UNIT
R_θJA	Junction-to-ambient thermal resistance	72.2	°C/W
R_θJC(top)	Junction-to-case(top) thermal resistance	17.5
R_θJB	Junction-to-board thermal resistance	35.0
ψ_JT	Junction-to-top characterization parameter	0.4
ψ_JB	Junction-to-board characterization parameter	34.5
R_θJC(bottom)	Junction-to-case(bottom) thermal resistance	n/a

7.5 Electrical Characteristics

All specifications at T_A = 25°C, AV_DD = CPV_DD = DV_DD = 3.3V, f_S = 48kHz, system clock = 512f_S and 24-bit data unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Resolution		16	24	32	Bits
Digital Input/Output
	Logic Family: 3.3V LVCMOS compatible
V_IH	Input logic level		0.7×DV_DD			V
V_IL	Input logic level				0.3×DV_DD	V
I_IH	Input logic current	V_IN = V_DD			10	µA
I_IL	Input logic current	V_IN = 0V			–10	µA
V_OH	Output logic level	I_OH = –4mA	0.8×DV_DD			V
V_OL	Output logic level	I_OL = 4mA			0.22×DV_DD	V
	Logic Family 1.8V LVCMOS compatible
V_IH	Input logic level		0.7×DV_DD			V
V_IL	Input logic level				0.3×DV_DD	V
I_IH	Input logic current	V_IN = V_DD			10	µA
I_IL	Input logic current	V_IN = 0V			–10	µA
V_OH	Output logic level	I_OH = –2mA	0.8×DV_DD			V
V_OL	Output logic level	I_OL = 2mA			0.22×DV_DD	V
Dynamic Performance (PCM Mode)⁽¹⁾⁽²⁾
	THD+N at -1 dB⁽²⁾	f_S = 48kHz		–94	–87	dB
		f_S = 96kHz		–94
		f_S = 192kHz		–94
	Dynamic range⁽²⁾	EIAJ, A-weighted, f_S = 48kHz	108	114
		EIAJ, A-weighted, f_S = 96kHz		114
		EIAJ, A-weighted, f_S = 192kHz		114
	Signal-to-noise ratio⁽²⁾	EIAJ, A-weighted, f_S = 48kHz		114
		EIAJ, A-weighted, f_S = 96kHz		114
		EIAJ, A-weighted, f_S = 192kHz		114
	Signal to noise ratio with analog mute⁽²⁾⁽³⁾	EIAJ, A-weighted, f_S = 48kHz	113	123
		EIAJ, A-weighted, f_S = 96kHz	113	123
		EIAJ, A-weighted, f_S = 192kHz	113	123
	Channel Separation	f_S = 48kHz	100 / 95	109 / 103		dB
		f_S = 96kHz	100 / 95	109 / 103
		f_S = 192kHz	100 / 95	109 / 103
Analog Output
	Single Ended Output voltage			2.1		V_RMS
	Differential Output Voltage			4.2		V_RMS
	Gain error		–6	±2.0	6	% of FSR
	Gain mismatch, channel-to-channel		–6	±0.5	6	% of FSR
	Bipolar zero error	At bipolar zero	–2	±1.0	2	mV
	Load impedance		5			kΩ
Filter Characteristics–1: Normal (8x)
	Pass band				0.45f_S	kHz
	Stop band		0.55f_S			kHz
	Stop band attenuation		–60			dB
	Pass-band ripple				±0.02	dB
	Delay time			20t_S		s
Filter Characteristics–2: Low Latency (8x)
	Pass band				0.47f_S	kHz
	Stop band		0.55f_S			kHz
	Stop band attenuation		–52			dB
	Pass-band ripple				±0.0001	dB
	Delay time			3.5t_S		s
Filter Characteristics–3: Asymmetric FIR (8x)
	Pass band				0.40f_S	kHz
	Stop band		0.72f_S			kHz
	Stop band attenuation		–52			dB
	Pass-band ripple				±0.05	dB
	Delay time			1.2t_S		s
Filter Characteristics–4: High-Attenuation (8x)
	Pass band				0.45f_S	kHz
	Stop band		0.45f_S			kHz
	Stop band attenuation			–100		dB
	Pass-band ripple				±0.0005	dB
	Delay time			33.7t_S		s
Power Supply Requirements
DV_DD	Digital supply voltage	Target DV_DD = 1.8V	1.65	1.8	1.95	VDC
DV_DD	Digital supply voltage	Target DV_DD = 3.3V	3.0	3.3	3.6	VDC
AV_DD	Analog supply voltage		3.0	3.3	3.6	VDC
CPV_DD	Charge-pump supply voltage		3.0	3.3	3.6	VDC
I_DD	DV_DD supply current at 1.8V	f_S = 48kHz, Input is Bipolar Zero data		11	14	mA
		f_S = 96kHz, Input is Bipolar Zero data		12
		f_S = 192kHz, Input is Bipolar Zero data		14
I_DD	DV_DD supply current at 1.8V	f_S = 48kHz, Input is 1kHz -1dBFS data		11	14	mA
		f_S = 96kHz, Input is 1kHz -1dBFS data		12
		f_S = 192kHz, Input is 1kHz -1dBFS data		14
I_DD	DV_DD supply current at 1.8V⁽⁴⁾	f_S = N/A, Power Down Mode		0.3	0.6	mA
I_DD	DV_DD supply current at 3.3V	f_S = 48kHz, Input is Bipolar Zero data		12	15	mA
		f_S = 96kHz, Input is Bipolar Zero data		13
		f_S = 192kHz, Input is Bipolar Zero data		15
I_DD	DV_DD supply current at 3.3V	f_S = 48kHz, Input is 1kHz -1dBFS data		12	15	mA
		f_S = 96kHz, Input is 1kHz -1dBFS data		13
		f_S = 192kHz, Input is 1kHz -1dBFS data		15
I_DD	DV_DD supply current at 3.3V⁽⁴⁾	f_S = N/A, Power Down Mode		0.5	0.8	mA
I_CC	AV_DD + CPV_DD Supply Current	f_S = 48kHz, Input is Bipolar Zero data		11	16	mA
		f_S = 96kHz, Input is Bipolar Zero data		11
		f_S = 192kHz, Input is Bipolar Zero data		11
I_CC	AV_DD + CPV_DD Supply Current	f_S = 48kHz, Input is 1kHz -1dBFS data		24	32	mA
		f_S = 96kHz, Input is 1kHz -1dBFS data		24
		f_S = 192kHz, Input is 1kHz -1dBFS data		24
I_CC	AV_DD + CPV_DD Supply Current⁽⁴⁾	f_S = N/A, Power Down Mode		0.2	0.4	mA
	Power Dissipation, DV_DD = 1.8V	f_S = 48kHz, Input is Bipolar Zero data		59.4	78	mW
		f_S = 96kHz, Input is Bipolar Zero data		61.2
		f_S = 192kHz, Input is Bipolar Zero data		64.8
	Power Dissipation, DV_DD = 1.8V	f_S = 48kHz, Input is 1kHz -1dBFS data		99	130.8	mW
		f_S = 96kHz, Input is 1kHz -1dBFS data		100.8
		f_S = 192kHz, Input is 1kHz -1dBFS data		104.4
	Power Dissipation, DV_DD = 1.8V⁽⁴⁾	f_S = N/A, Power Down Mode		1.2		mW
	Power Dissipation, DV_DD = 3.3V	f_S = 48kHz, Input is Bipolar Zero data		79.2	103	mW
		f_S = 96kHz, Input is Bipolar Zero data		82.5
		f_S = 192kHz, Input is Bipolar Zero data		89.1
	Power Dissipation, DV_DD = 3.3V	f_S = 48kHz, Input is 1kHz -1dBFS data		118.8	155	mW
		f_S = 96kHz, Input is 1kHz -1dBFS data		122.1
		f_S = 192kHz, Input is 1kHz -1dBFS data		128.7
	Power Dissipation, DV_DD = 3.3V⁽⁴⁾	f_S = N/A, Power Down Mode		2.3	4.0	mW

(1) Filter condition: THD+N: 20Hz HPF, 20kHz AES17 LPF Dynamic range: 20Hz HPF, 20kHz AES17 LPF, A-weighted Signal-to-noise ratio: 20Hz HPF, 20kHz AES17 LPF, A-weighted Channel separation: 20Hz HPF, 20kHz AES17 LPF Analog performance specifications are measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the RMS mode.

(2) Output load is 10kΩ, with 470Ω output resistor and a 2.2nF shunt capacitor (see recommended output filter).

(3) Assert XSMT or both L-ch and R-ch PCM data are BPZ

(4) Power Down Mode, with LRCK, BCK, and SCK halted at Low level.

(5) One sample time si defined as the reciprocal of the sampling frequency. 1t_S = 1/f_S

(6) With the appropriate P coefficient setting, the PLL accepts up to 50MHz. This clock is then divided to meet the ≤ 20MHz requirement. See PLL Calculation.

7.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
Data Format (PCM Mode)
	Audio data interface format		I²S, left justified, right justified and TDM
	Audio data bit length		16, 20, 24, 32-bit acceptable
	Audio data format		MSB First, 2s Complement
f_S⁽⁵⁾	Sampling frequency		8	384	kHz
Clocks
	System clock frequency		64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or 3072 f_SCK, up to 50Mhz
	PLL Input Frequency ⁽⁶⁾	Clock divider uses fractional divide D > 0, P=1	6.7	20	MHz
	PLL Input Frequency ⁽⁶⁾	Clock divider uses integer divide D = 0, P=1	1	20	MHz

7.7 Timing Requirements: SCK Input

Figure 4 shows the timing requirements for the system clock input. For optimal performance, use a clock source with low phase jitter and noise.

			MIN	MAX	UNIT
t_SCY	System clock pulse cycle time		20	1000	ns
t_SCKH	System clock pulse width, High	DVDD = 1.8V	8		ns
t_SCKH	System clock pulse width, High	DVDD = 3.3V	9		ns
t_SCKL	System clock pulse width, Low	DVDD = 1.8V	8		ns
t_SCKL	System clock pulse width, Low	DVDD = 3.3V	9		ns

Figure 4. Timing Requirements for SCK Input

7.8 Timing Requirements: PCM Audio Data

		MIN	MAX	UNIT
t_BCY	BCK Pulse Cycle Time	40		ns
t_BCL	BCK Pulse Width LOW	16		ns
t_BCH	BCK Pulse Width HIGH	16		ns
t_BL	BCK Rising Edge to LRCK Edge	8		ns
t_BCK	BCK frequency at DVDD = 3.3V		24.576	MHz
t_BCK(1.8V)	BCK frequency at DVDD = 1.8V		12.288	MHz
t_LB	LRCK Edge to BCK Rising Edge	8		ns
t_DS	DATA Set Up Time	8		ns
t_DH	DATA Hold Time	8		ns
t_DOD	DATA delay time from BCK falling edge		15	ns

Figure 5. PCM5242 Serial Audio Timing - Slave

In software mode, the PCM5242 can act as an I²S master, generating BCK and LRCK as outputs from the SCK input.

Table 3. I²S Master Mode Registers

Register	Function
Page0, Register 9, D(0), D(4), and D(5)	I²S Master mode select
Register 32, D(6:0)	BCK divider and LRCK divider
Register 33, D(7:0)	BCK divider and LRCK divider

The I²S master timing is shown in Figure 6.

		MIN	MAX	UNIT
t_BCY	BCK Pulse Cycle Time	40		ns
t_BCL	BCK Pulse Width LOW	16		ns
t_BCH	BCK Pulse Width HIGH	16		ns
t_BCK	BCK frequency at DVDD = 3.3V		24.576	MHz
t_BCK(1.8V)	BCK frequency at DVDD = 1.8V		12.288	MHz
t_LRD	LRCKx delay time from BCKx falling edge	–10	20	ns
t_DS	DATA Set Up Time	8		ns
t_DH	DATA Hold Time	8		ns
t_DOD	DATA delay time from BCK falling edge at DVDD = 3.3V		15	ns
t_DOD(1.8V)	DATA delay time from BCK falling edge at DVDD = 1.8V		20	ns