ZHCSDH3 November   2014 PCM5252

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1. 6.1 Control Mode Effect On Pin Assignments
    2. 6.2 Pin Assignments
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics
    7. 7.7  Timing Requirements: SCK Input
    8. 7.8  Timing Requirements: PCM Audio Data
    9. 7.9  Timing Requirements: I2S Master, See
    10. 7.10 Timing Requirements: XSMT
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Terminology
      2. 8.3.2 Audio Data Interface
        1. 8.3.2.1 Audio Serial Interface
        2. 8.3.2.2 PCM Audio Data Formats
        3. 8.3.2.3 Zero Data Detect
      3. 8.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
      4. 8.3.4 Audio Processing
        1. 8.3.4.1  PCM5252 Audio Processing Options
          1. 8.3.4.1.1 Overview
          2. 8.3.4.1.2 miniDSP Instruction Register
          3. 8.3.4.1.3 Digital Output
          4. 8.3.4.1.4 Software
        2. 8.3.4.2  Interpolation Filter
        3. 8.3.4.3  Overview
        4. 8.3.4.4  Smart SOA
        5. 8.3.4.5  Smart BASS
        6. 8.3.4.6  Smart Protection
        7. 8.3.4.7  Implementing a Real World Design
        8. 8.3.4.8  Digital Output
        9. 8.3.4.9  Software
        10. 8.3.4.10 Process Flow
      5. 8.3.5 DAC and Differential Analog Outputs
        1. 8.3.5.1 Analog Outputs
        2. 8.3.5.2 Choosing Between VREF and VCOM Modes
          1. 8.3.5.2.1 Voltage Reference and Output Levels
          2. 8.3.5.2.2 Mode Switching Sequence, from VREF Mode to VCOM Mode
        3. 8.3.5.3 Digital Volume Control
          1. 8.3.5.3.1 Emergency Ramp-Down
        4. 8.3.5.4 Analog Gain Control
      6. 8.3.6 Reset and System Clock Functions
        1. 8.3.6.1 Clocking Overview
        2. 8.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)
        3. 8.3.6.3 Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)
        4. 8.3.6.4 Clock Generation Using the PLL
        5. 8.3.6.5 PLL Calculation
          1. 8.3.6.5.1 Examples:
            1. 8.3.6.5.1.1 Recommended PLL Settings
        6. 8.3.6.6 Clock Master Mode from Audio Rate Master Clock
        7. 8.3.6.7 Clock Master from a Non-Audio Rate Master Clock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Choosing a Control Mode
        1. 8.4.1.1 Software Control
          1. 8.4.1.1.1 SPI Interface
            1. 8.4.1.1.1.1 Register Read and Write Operation
          2. 8.4.1.1.2 I2C Interface
            1. 8.4.1.1.2.1 Slave Address
            2. 8.4.1.1.2.2 Register Address Auto-Increment Mode
            3. 8.4.1.1.2.3 Packet Protocol
            4. 8.4.1.1.2.4 Write Register
            5. 8.4.1.1.2.5 Read Register
            6. 8.4.1.1.2.6 Timing Characteristics
      2. 8.4.2 VREF and VCOM Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 High Fidelity Smartphone Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Initialization Script
        3. 9.2.1.3 Application Performance Plot
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Distribution and Requirements
    2. 10.2 Recommended Powerdown Sequence
      1. 10.2.1 XSMT = 0
      2. 10.2.2 Clock Error Detect
      3. 10.2.3 Planned Shutdown
      4. 10.2.4 Unplanned Shutdown
    3. 10.3 External Power Sense Undervoltage Protection Mode
    4. 10.4 Power-On Reset Function
      1. 10.4.1 Power-On Reset, DVDD 3.3-V Supply
      2. 10.4.2 Power-On Reset, DVDD 1.8-V Supply
    5. 10.5 PCM5252 Power Modes
      1. 10.5.1 Setting Digital Power Supplies and I/O Voltage Rails
      2. 10.5.2 Power Save Modes
      3. 10.5.3 Power Save Parameter Programming
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Programming
    1. 12.1 Coefficient Data Formats
    2. 12.2 Power Down and Reset Behavior
  13. 13Register Maps
    1. 13.1 PCM5252 Register Map
      1. 13.1.1 Detailed Register Descriptions
        1. 13.1.1.1 Register Map Summary
        2. 13.1.1.2 Page 0 Registers
        3. 13.1.1.3 Page 1 Registers
        4. 13.1.1.4 Page 44 Registers
        5. 13.1.1.5 Page 253 Registers
      2. 13.1.2 PLL Tables for Software Controlled Devices
  14. 14器件和文档支持
    1. 14.1 社区资源
    2. 14.2 商标
    3. 14.3 静电放电警告
  15. 15机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

13 Register Maps

13.1 PCM5252 Register Map

In any page, register 0 is the Page Select Register. The register value selects the Register Page from 0 to 255 for next read or write command.

Table 39. Register Map Overview

REGISTER NUMBER DESCRIPTION
Page 0
0 Page select register
1 Analog control register
2 Standby, Powerdown requests
3 Mute
4 PLL Lock Flag, PLL enable
5 Reserved
6 SPI MISO function select
7 De-emphasis enable, SDOUT select
8 GPIO enables
9 BCK, LRCLK configuration
10 DSP GPIO Input
11 Reserved
12 Master mode BCK, LRCLK reset
13 PLL clock source select
14 - 19 Reserved
20 - 24 PLL dividers
25, 26 Reserved
27 DSP clock divider
28 DAC clock divider
29 NCP clock divider
30 OSR clock divider
31 Reserved
32, 33 Master mode dividers
34 fS speed mode
35, 36 IDAC (number of DSP clock cycles available in one audio frame)
37 Ignore various errors
38,39 Reserved
40, 41 I2S configuration
42 DAC data path
43 DSP program selection
44 Clock missing detection period
59 Auto mute time
60 - 64 Digital volume
65 Auto mute
75 - 79 Reserved
80 - 85 GPIOn output selection
86, 87 GPIO control
88, 89 Reserved
90 DSP overflow
91 - 94 Sample rate status
95 - 107 Reserved
108 Analog mute monitor
109 - 118 Reserved
119 GPIO input
120 Auto Mute flags
121 Reserved
Page 1
1 Output amplitude type
2 Analog gain control
3, 4 Reserved
5 Undervoltage protection
6 Analog mute control
7 Analog gain boost
8, 9 VCOM configuration
Page 44
1 Coefficient memory (CRAM) control
Pages 44 - 52 Coefficient buffer - A (256 coeffs x 24 bits) : See Table 41
Pages 62 - 70 Coefficient buffer - B (256 coeffs x 24 bits) : See Table 42
71 - 252 Reserved
Pages 152 - 186 Instruction buffer (1024 instruction x 25 bits), I512 - I1023 are reserved.: See Table 43
Pages 187 - 252 Reserved
Page 253
63, 64 Clock Flex Mode
Pages 254 - 255 Reserved

The PCM5252 has a register map split into multiple pages. Pages 0 and 1 control of the DAC and other on-chip peripherals. Pages 44 through 52 are used for Coefficient A memory, while Pages 62-70 are coefficient B memory. Pages 152-186 contain the miniDSP instruction memory. Page 253 is where the Clock Flex Mode register is located.

Table 40. PCM5252 Register Page Structure

Page: 0 1 2-43 44-52 53-61 62-70 71-151 152-186 187-252 253 254-255
Func: Control Analog Control Reserved Coeffient A Reserved Coeffient B Reserved Instruction Reserved Clock Flex Reserved
Desc: General Control and Configuration Analog Control 256 24-bit coefficients,
30 coefficients per page,
4 registers per coefficient		 256 24-bit coefficients,
30 coefficients per page,
4 registers per coefficient		 1024 24-bit instructions,
30 instructions per page,
4 registers per instruction		 Clock Flex Mode

Table 41. Coefficient Buffer-A Map

COEFF NO PAGE NO BASE REGISTER BASE REGISTER + 0 BASE REGISTER + 1 BASE REGISTER + 2 BASE REGISTER + 3
C0 44 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C1 44 12 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C29 44 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C30 45 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C59 45 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C60 46 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C89 46 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C90 47 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C119 47 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C120 48 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C149 48 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C150 49 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C179 49 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C180 50 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C209 50 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C210 51 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C239 51 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C240 52 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C255 52 68 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.

Table 42. Coefficient Buffer-B Map

COEFF NO PAGE NO BASE REGISTER BASE REGISTER + 0 BASE REGISTER + 1 BASE REGISTER + 2 BASE REGISTER + 3
C0 62 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C1 62 12 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C29 62 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C30 63 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C59 63 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C60 64 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C89 64 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C90 65 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C119 65 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C120 66 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C149 66 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C150 67 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C179 67 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C180 68 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C209 68 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C210 69 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C239 69 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
C240 70 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.
.. .. .. .. .. .. ..
C255 70 68 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.

Table 43. miniDSP Instruction Map

COEFF NO PAGE NO BASE REGISTER BASE REGISTER + 0 BASE REGISTER + 1 BASE REGISTER + 2 BASE REGISTER + 3
I0 152 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I1 152 12 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I29 152 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I30 153 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I59 153 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I60 154 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I89 154 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I90 155 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I119 155 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I120 156 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I149 156 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I150 157 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I179 157 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I180 158 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I209 158 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I210 159 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I239 159 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I240 160 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I269 160 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I270 161 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I299 161 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I300 162 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I329 162 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I330 163 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I359 163 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I360 164 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I389 164 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I390 165 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I419 165 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I420 166 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I449 166 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I450 167 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I479 167 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I480 168 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I509 168 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I510 169 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
I511 169 12 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0)
.. .. .. .. .. .. ..
I539 169 124 Reserved. Reserved. Reserved. Reserved.
I540 170 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I569 170 124 Reserved. Reserved. Reserved. Reserved.
I570 171 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I599 171 124 Reserved. Reserved. Reserved. Reserved.
I600 172 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I629 172 124 Reserved. Reserved. Reserved. Reserved.
I630 173 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I659 173 124 Reserved. Reserved. Reserved. Reserved.
I660 174 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I689 174 124 Reserved. Reserved. Reserved. Reserved.
I690 175 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I719 175 124 Reserved. Reserved. Reserved. Reserved.
I720 176 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I749 176 124 Reserved. Reserved. Reserved. Reserved.
I750 177 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I779 177 124 Reserved. Reserved. Reserved. Reserved.
I780 178 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I809 178 124 Reserved. Reserved. Reserved. Reserved.
I810 179 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I839 179 124 Reserved. Reserved. Reserved. Reserved.
I840 180 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I869 180 124 Reserved. Reserved. Reserved. Reserved.
I870 181 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I899 181 124 Reserved. Reserved. Reserved. Reserved.
I900 182 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I929 182 124 Reserved. Reserved. Reserved. Reserved.
I930 183 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I959 183 124 Reserved. Reserved. Reserved. Reserved.
I960 184 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I989 184 124 Reserved. Reserved. Reserved. Reserved.
I990 185 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I1019 185 124 Reserved. Reserved. Reserved. Reserved.
I1020 186 8 Reserved. Reserved. Reserved. Reserved.
.. .. .. .. .. .. ..
I1023 186 20 Reserved. Reserved. Reserved. Reserved.

13.1.1 Detailed Register Descriptions

13.1.1.1 Register Map Summary

Table 44. Register Map Summary

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
Page 0
1 01 RSV RSV RSV RSTM RSV RSV RSV RSTR
2 02 RSV RSV RSV RQST RSV RSV RSV RQPD
3 03 RSV RSV RSV RQML RSV RSV RSV RQMR
4 04 RSV RSV RSV PLCK RSV RSV RSV PLLE
6 06 RSV RSV RSV RSV RSV RSV FSMI1 FSMI0
7 07 RSV RSV RSV DEMP RSV RSV RSV SDSL
8 08 RSV RSV G6OE G5OE G4OE G3OE G2OE G1OE
9 09 RSV RSV BCKP BCKO RSV RSV RSV LRKO
10 0A DSPG7 DSPG6 DSPG5 DSPG4 DSPG3 DSPG2 DSPG1 DSPG0
12 0C RSV RSV RSV RSV RSV RSV RBCK RLRK
13 0D RSV SREF2 SREF1 SREF0 RSV RSV RSV RSV
14 0E RSV SDAC2 SDAC1 SDAC0 RSV RSV RSV RSV
18 12 RSV RSV RSV RSV RSV GREF2 GREF1 GREF0
19 13 RSV RSV RSV RSV RSV RSV RSV RQSY
20 14 RSV RSV RSV RSV PPDV3 PPDV2 PPDV1 PPDV0
21 15 RSV RSV PJDV5 PJDV4 PJDV3 PJDV2 PJDV1 PJDV0
22 16 RSV RSV PDDV13 PDDV12 PDDV11 PDDV10 PDDV9 PDDV8
23 17 PDDV7 PDDV6 PDDV5 PDDV4 PDDV3 PDDV2 PDDV1 PDDV0
24 18 RSV RSV RSV RSV PRDV3 PRDV2 PRDV1 PRDV0
27 1B RSV DDSP6 DDSP5 DDSP4 DDSP3 DDSP2 DDSP1 DDSP0
28 1C RSV DDAC6 DDAC5 DDAC4 DDAC3 DDAC2 DDAC1 DDAC0
29 1D RSV DNCP6 DNCP5 DNCP4 DNCP3 DNCP2 DNCP1 DNCP0
30 1E RSV DOSR6 DOSR5 DOSR4 DOSR3 DOSR2 DOSR1 DOSR0
32 20 RSV DBCK6 DBCK5 DBCK4 DBCK3 DBCK2 DBCK1 DBCK0
33 21 DLRK7 DLRK6 DLRK5 DLRK4 DLRK3 DLRK2 DLRK1 DLRK0
34 22 RSV RSV RSV I16E RSV RSV FSSP1 FSSP0
35 23 IDAC15 IDAC14 IDAC13 IDAC12 IDAC11 IDAC10 IDAC9 IDAC8
36 24 IDAC7 IDAC6 IDAC5 IDAC4 IDAC3 IDAC2 IDAC1 IDAC0
37 25 RSV IDFS IDBK IDSK IDCH IDCM DCAS IPLK
40 28 RSV RSV AFMT1 AFMT0 RSV RSV ALEN1 ALEN0
41 29 AOFS7 AOFS6 AOFS5 AOFS4 AOFS3 AOFS2 AOFS1 AOFS0
42 2A RSV RSV AUPL1 AUPL0 RSV RSV AUPR1 AUPR0
43 2B RSV RSV RSV PSEL4 PSEL3 PSEL2 PSEL1 PSEL0
44 2C RSV RSV RSV RSV RSV CMDP2 CMDP1 CMDP0
59 3B RSV AMTL2 AMTL1 AMTL0 RSV AMTR2 AMTR1 AMTR0
60 3C RSV RSV RSV RSV RSV RSV PCTL1 PCTL0
61 3D VOLL7 VOLL6 VOLL5 VOLL4 VOLL3 VOLL2 VOLL1 VOLL0
62 3E VOLR7 VOLR6 VOLR5 VOLR4 VOLR3 VOLR2 VOLR1 VOLR0
63 3F VNDF1 VNDF0 VNDS1 VNDS0 VNUF1 VNUF0 VNUS1 VNUS0
64 40 VEDF1 VEDF0 VEDS1 VEDS0 RSV RSV RSV RSV
65 41 RSV RSV RSV RSV RSV ACTL2 AMLE1 AMRE0
80 50 RSV RSV RSV G1SL4 G1SL3 G1SL2 G1SL1 G1SL0
81 51 RSV RSV RSV G2SL4 G2SL3 G2SL2 G2SL1 G2SL0
82 52 RSV RSV RSV G3SL4 G3SL3 G3SL2 G3SL1 G3SL0
83 53 RSV RSV RSV G4SL4 G4SL3 G4SL2 G4SL1 G4SL0
84 54 RSV RSV RSV G5SL4 G5SL3 G5SL2 G5SL1 G5SL0
85 55 RSV RSV RSV G6SL4 G6SL3 G6SL2 G6SL1 G6SL0
86 56 RSV RSV GOUT5 GOUT4 GOUT3 GOUT2 GOUT1 GOUT0
87 57 RSV RSV GINV5 GINV4 GINV3 GINV2 GINV1 GINV0
90 5A RSV RSV RSV L1OV R1OV L2OV R2OV SFOV
91 5B RSV DTFS2 DTFS1 DTFS0 DTSR3 DTSR2 DTSR1 DTSR0
92 5C RSV RSV RSV RSV RSV RSV RSV DTBR8
93 5D DTBR7 DTBR6 DTBR5 DTBR4 DTBR3 DTBR2 DTBR1 DTBR0
94 5E RSV CDST PLL-L LrckBck fS-SCKr SCKval BCKval fSval
95 5F RSV RSV RSV LTSH RSV CKMF CSRF CERF
108 6C RSV RSV RSV RSV RSV RSV AMLM AMRM
109 6D RSV RSV RSV SDTM RSV RSV RSV SHTM
114 72 RSV RSV RSV RSV RSV RSV MTST1 MTST0
115 73 RSV RSV RSV RSV RSV RSV FSMM1 FSMM0
118 76 BOTM RSV RSV RSV PSTM3 PSTM2 PSTM1 PSTM0
119 77 RSV RSV GPIN5 GPIN4 GPIN3 GPIN2 GPIN1 RSV
120 78 RSV RSV RSV AMFL RSV RSV RSV AMFR
121 79 RSV RSV RSV RSV RSV RSV RSV DAMD
122 7A RSV RSV RSV RSV RSV RSV RSV EIFM
123 7B RSV G1MC2 G1MC1 G1MC0 RSV G2MC2 G2MC1 G2MC0
124 7C RSV G3MC2 G3MC1 G3MC0 RSV G4MC2 G4MC1 G4MC0
125 7D RSV G5MC2 G5MC1 G5MC0 RSV G6MC2 G6MC1 G6MC0
Page 1
Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
1 01 RSV RSV RSV RSV RSV RSV RSV OSEL
2 02 RSV RSV RSV LAGN RSV RSV RSV RAGN
5 05 RSV RSV RSV RSV RSV RSV UEPD UIPD
6 06 RSV RSV RSV RSV RSV RSV RSV AMCT
7 07 RSV RSV RSV AGBL RSV RSV RSV AGBR
8 08 RSV RSV RSV RSV RSV RSV RSV RCMF
9 09 RSV RSV RSV RSV RSV RSV RSV VCPD
Page 44
Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
1 01 RSV RSV RSV RSV ACRM AMDC ACRS ACSW
Page 253
Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
63 3F PLLFLEX17 PLLFLEX16 PLLFLEX15 PLLFLEX14 PLLFLEX13 PLLFLEX12 PLLFLEX11 PLLFLEX10
64 40 PLLFLEX27 PLLFLEX26 PLLFLEX25 PLLFLEX24 PLLFLEX23 PLLFLEX22 PLLFLEX21 PLLFLEX20

13.1.1.2 Page 0 Registers

Table 45. Page 0 / Register 1

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
1 01 RSV RSV RSV RSTM RSV RSV RSV RSTR
Reset Value 0 0
RSV Reserved
Reserved. Do not access.
RSTM Reset Modules
This bit resets the interpolation filter and the DAC modules. Since the DSP is also reset, the coeffient RAM content will also be cleared by the DSP. This bit is auto cleared and can be set only in standby mode.
Default value: 0
0: Normal
1: Reset modules
RSTR Reset Registers
This bit resets the mode registers back to their initial values. The RAM content is not cleared, but the execution source will be back to ROM. This bit is auto cleared and must be set only when the DAC is in standby mode (resetting registers when the DAC is running is prohibited and not supported).
Default value: 0
0: Normal
1: Reset mode registers

Table 46. Page 0 / Register 2

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
2 02 RSV RSV RSV RQST RSV RSV RSV RQPD
Reset Value 0 0
RSV Reserved
Reserved. Do not access.
RQST Standby Request
When this bit is set, the DAC will be forced into a system standby mode, which is also the mode the system enters in the case of clock errors. In this mode, most subsystems will be powered down but the charge pump and digital power supply.
Default value: 0
0: Normal operation
1: Standby mode
RQPD Powerdown Request
When this bit is set, the DAC will be forced into powerdown mode, in which the power consumption would be minimum as the charge pump is also powered down. However, it will take longer to restart from this mode. This mode has higher precedence than the standby mode, that is, setting this bit along with bit 4 for standby mode will result in the DAC going into powerdown mode.
Default value: 0
0: Normal operation
1: Powerdown mode

Table 47. Page 0 / Register 3

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
3 03 RSV RSV RSV RQML RSV RSV RSV RQMR
Reset Value 0 0
RSV Reserved
Reserved. Do not access.
RQML Mute Left Channel
This bit issues soft mute request for the left channel. The volume will be smoothly ramped down/up to avoid pop/click noise.
Default value: 0
0: Normal volume
1: Mute
RQMR Mute Right Channel
This bit issues soft mute request for the right channel. The volume will be smoothly ramped down/up to avoid pop/click noise.
Default value: 0
0: Normal volume
1: Mute

Table 48. Page 0 / Register 4

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
4 04 RSV RSV RSV PLCK RSV RSV RSV PLLE
Reset Value 1
RSV Reserved
Reserved. Do not access.
PLCK PLL Lock Flag (Read Only)
This bit indicates whether the PLL is locked or not. When the PLL is disabled this bit always shows that the PLL is not locked.
0: The PLL is locked
1: The PLL is not locked
PLLE PLL Enable
This bit enables or disables the internal PLL. When PLL is disabled, the master clock will be switched to the SCK.
Default value: 1
0: Disable PLL
1: Enable PLL

Table 49. Page 0 / Register 6

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
6 06 RSV RSV RSV RSV RSV RSV FSMI1 FSMI0
Reset Value 0 0
RSV Reserved
Reserved. Do not access.
FSMI[1:0] SPI MISO function sel
These bits select the function of the SPI_MISO pin when in SPI mode. If the pin is set as GPIO, register readout via SPI is not possible.
Default value: 00
00: SPI_MISO
01: GPIO1
Others: Reserved (Do not set)

Table 50. Page 0 / Register 7

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
7 07 RSV RSV RSV DEMP RSV RSV RSV SDSL
Reset Value 0 0
RSV Reserved
Reserved. Do not access.
DEMP De-Emphasis Enable
This bit enables or disables the de-emphasis filter. The default coefficients are for 44.1kHz sampling rate, but can be changed by reprogramming the appropriate coeffients in RAM.
Default value: 0
0: De-emphasis filter is disabled
1: De-emphasis filter is enabled
SDSL SDOUT Select
This bit selects what is being output as SDOUT via GPIO pins.
Default value: 0
0: SDOUT is the DSP output (post-processing)
1: SDOUT is the DSP input (pre-processing)

Table 51. Page 0 / Register 8

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
8 08 RSV RSV G6OE G5OE G4OE G3OE G2OE G1OE
Reset Value 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
G6OE GPIO6 Output Enable
This bit sets the direction of the GPIO6 pin
Default value: 0
0: GPIO6 is input
1: GPIO6 is output
G5OE GPIO5 Output Enable
This bit sets the direction of the GPIO5 pin
Default value: 0
0: GPIO5 is input
1: GPIO5 is output
G4OE GPIO4 Output Enable
This bit sets the direction of the GPIO4 pin
Default value: 0
0: GPIO4 is input
1: GPIO4 is output
G3OE GPIO3 Output Enable
This bit sets the direction of the GPIO3 pin
Default value: 0
0: GPIO3 is input
1: GPIO3 is output
G2OE GPIO2 Output Enable
This bit sets the direction of the GPIO2 pin
Default value: 0
0: GPIO2 is input
1: GPIO2 is output
G1OE GPIO1 Output Enable
This bit sets the direction of the GPIO1 pin
Default value: 0
0: GPIO1 is input
1: GPIO1 is output

Table 52. Page 0 / Register 9

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
9 09 RSV RSV BCKP BCKO RSV RSV RSV LRKO
Reset Value 0 0 0
RSV Reserved
Reserved. Do not access.
BCKP BCK Polarity
This bit sets the inverted BCK mode. In inverted BCK mode, the DAC assumes that the LRCK and DIN edges are aligned to the rising edge of the BCK. Normally they are assumed to be aligned to the falling edge of the BCK.
Default value: 0
0: Normal BCK mode
1: Inverted BCK mode
BCKO BCK Output Enable
This bit sets the BCK pin direction to output for I2S master mode operation. In I2S master mode the PCM5xxx outputs the reference BCK and LRCK, and the external source device provides the DIN according to these clocks. Use Page 0 / Register 32 to program the division factor of the SCK to yield the desired BCK rate (normally 64FS)
Default value: 0
0: BCK is input (I2S slave mode)
1: BCK is output (I2S master mode)
LRKO LRCLK Output Enable
This bit sets the LRCK pin direction to output for I2S master mode operation. In I2S master mode the PCM5xxx outputs the reference BCK and LRCK, and the external source device provides the DIN according to these clocks. Use Page 0 / Register 33 to program the division factor of the BCK to yield 1FS for LRCK.
Default value: 0
0: LRCK is input (I2S slave mode)
1: LRCK is output (I2S master mode)

Table 53. Page 0 / Register 10

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
10 0A DSPG7 DSPG6 DSPG5 DSPG4 DSPG3 DSPG2 DSPG1 DSPG0
Reset Value 0 0 0 0 0 0 0 0
DSPG[7:0] DSP GPIO Input
The DSP accepts a 24-bit external control signals input. The value set in this register will go to bit 16:8 of this external input.
Default value: 00000000

Table 54. Page 0 / Register 12

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
12 0C RSV RSV RSV RSV RSV RSV RBCK RLRK
Reset Value 0 0
RSV Reserved
Reserved. Do not access.
RBCK Master Mode BCK Divider Reset
This bit, when set to 0, will reset the SCK divider to generate BCK clock for I2S master mode. To use I2S master mode, the divider must be enabled and programmed properly.
Default value: 0
0: Master mode BCK clock divider is reset
1: Master mode BCK clock divider is functional
RLRK Master Mode LRCK Divider Reset
This bit, when set to 0, will reset the BCK divider to generate LRCK clock for I2S master mode. To use I2S master mode, the divider must be enabled and programmed properly.
Default value: 0
0: Master mode LRCK clock divider is reset
1: Master mode LRCK clock divider is functional

Table 55. Page 0 / Register 13

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
13 0D RSV SREF2 SREF1 SREF0 RSV RSV RSV RSV
Reset Value 0 0 0
RSV Reserved
Reserved. Do not access.
SREF[2:0] PLL Reference
This bit select the source clock for internal PLL. This bit is ignored and overriden in clock auto set mode.
Default value: 000
000: The PLL reference clock is SCK
001: The PLL reference clock is BCK
010: Reserved
011: The PLL reference clock is GPIO (selected using Page 0 / Register 18)
others: Reserved (PLL reference is muted)
SREF PLL Reference
Default value: 0

Table 56. Page 0 / Register 14

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
14 0E RSV SDAC2 SDAC1 SDAC0 RSV RSV RSV RSV
Reset Value 0 0 0
RSV Reserved
Reserved. Do not access.
SDAC[2:0] DAC clock source
These bits select the source clock for DAC clock divider.
Default value: 000
This Register requires use of the Clock Flex Register
000: Master clock (PLL/SCK and OSC auto-select)
001: PLL clock
010: Reserved
011: SCK clock
100: BCK clock
others: Reserved (muted)

Table 57. Page 0 / Register 18

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
18 12 RSV RSV RSV RSV RSV GREF2 GREF1 GREF0
Reset Value 0 0 0
RSV Reserved
Reserved. Do not access.
GREF[2:0] GPIO Source for PLL reference clk
These bits select the GPIO pins as clock input source when GPIO is selected as the PLL reference clock source.
Default value: 000
This register requires use of the Clock Flex Register.000: GPIO1
001: GPIO2
010: GPIO3
011: GPIO4
100: GPIO5
101: GPIO6
others: Reserved (muted)

Table 58. Page 0 / Register 19

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
19 13 RSV RSV RSV RSV RSV RSV RSV RQSY
Reset Value 0
RSV Reserved
Reserved. Do not access.
RQSY Sync request
This bit, when set to 1 will issue the clock resynchronization by synchronously resets the DAC, CP and OSR clocks. The actual clock resynchronization takes place when this bit is set back to 0, where the DAC, CP and OSR clocks are resumed at the beginning of the audio frame.
Default value: 0
0: Resume DAC, CP and OSR clocks synchronized to the beginning of audio frame
1: Halt DAC, CP and OSR clocks as the beginning of resynchronization process

Table 59. Page 0 / Register 20

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
20 14 RSV RSV RSV RSV PPDV3 PPDV2 PPDV1 PPDV0
Reset Value 0 0 0 0
RSV Reserved
Reserved. Do not access.
PPDV[3:0] PLL P
These bits set the PLL divider P factor. These bits are ignored in clock auto set mode.
Default value: 0000
0000: P=1
0001: P=2
...
1110: P=15
1111: Prohibited (do not set this value)

Table 60. Page 0 / Register 21

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
21 15 RSV RSV PJDV5 PJDV4 PJDV3 PJDV2 PJDV1 PJDV0
Reset Value 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
PJDV[5:0] PLL J
These bits set the J part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode.
Default value: 000000
000000: Prohibited (do not set this value)
000001: J=1
000010: J=2
...
111111: J=63

Table 61. Page 0 / Register 22

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
22 16 RSV RSV PDDV13 PDDV12 PDDV11 PDDV10 PDDV9 PDDV8
Reset Value 0 0 0 0 0 0

Table 62. Page 0 / Register 23

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
23 17 PDDV7 PDDV6 PDDV5 PDDV4 PDDV3 PDDV2 PDDV1 PDDV0
Reset Value 0 0 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
PDDV[13:0] PLL D (MSB)
These bits set the D part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode.
Default value: 00000000000000
0 (in decimal): D=0000
1 (in decimal): D=0001
...
9999 (in decimal): D=9999
others: Prohibited (do not set)

Table 63. Page 0 / Register 24

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
24 18 RSV RSV RSV RSV PRDV3 PRDV2 PRDV1 PRDV0
Reset Value 0 0 0 0
RSV Reserved
Reserved. Do not access.
PRDV[3:0] PLL R
These bits set the R part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode.
Default value: 0000
0000: R=1
0001: R=2
...
1111: R=16

Table 64. Page 0 / Register 27

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
27 1B RSV DDSP6 DDSP5 DDSP4 DDSP3 DDSP2 DDSP1 DDSP0
Reset Value 0 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
DDSP[6:0] DSP Clock Divider
These bits set the source clock divider value for the DSP clock. These bits are ignored in clock auto set mode.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128

Table 65. Page 0 / Register 28

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
28 1C RSV DDAC6 DDAC5 DDAC4 DDAC3 DDAC2 DDAC1 DDAC0
Reset Value 0 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
DDAC[6:0] DAC Clock Divider
These bits set the source clock divider value for the DAC clock. These bits are ignored in clock auto set mode.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128

Table 66. Page 0 / Register 29

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
29 1D RSV DNCP6 DNCP5 DNCP4 DNCP3 DNCP2 DNCP1 DNCP0
Reset Value 0 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
DNCP[6:0] NCP Clock Divider
These bits set the source clock divider value for the CP clock. These bits are ignored in clock auto set mode.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128

Table 67. Page 0 / Register 30

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
30 1E RSV DOSR6 DOSR5 DOSR4 DOSR3 DOSR2 DOSR1 DOSR0
Reset Value 0 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
DOSR[6:0] OSR Clock Divider
These bits set the source clock divider value for the OSR clock. These bits are ignored in clock auto set mode.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128

Table 68. Page 0 / Register 32

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
32 20 RSV DBCK6 DBCK5 DBCK4 DBCK3 DBCK2 DBCK1 DBCK0
Reset Value 0 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
DBCK[6:0] Master Mode BCK Divider
These bits set the SCK divider value to generate I2S master BCK clock.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128

Table 69. Page 0 / Register 33

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
33 21 DLRK7 DLRK6 DLRK5 DLRK4 DLRK3 DLRK2 DLRK1 DLRK0
Reset Value 0 0 0 0 0 0 0 0
DLRK[7:0] Master Mode LRCK Divider
These bits set the I2S master BCK clock divider value to generate I2S master LRCK clock.
Default value: 00000000
00000000: Divide by 1
00000001: Divide by 2
...
11111111: Divide by 256

Table 70. Page 0 / Register 34

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
34 22 RSV RSV RSV I16E RSV RSV FSSP1 FSSP0
Reset Value 0 0 0
RSV Reserved
Reserved. Do not access.
I16E 16x Interpolation
This bit enables or disables the 16x interpolation mode
Default value: 0
0: 8x interpolation
1: 16x interpolation
FSSP[1:0] FS Speed Mode
These bits select the FS operation mode, which must be set according to the current audio sampling rate. These bits are ignored in clock auto set mode.
Default value: 00
00: Single speed (FS ≤ 48 kHz)
01: Double speed (48 kHz < FS ≤ 96 kHz)
10: Quad speed (96 kHz < FS ≤ 192 kHz)
11: Octal speed (192 kHz < FS ≤ 384 kHz)

Table 71. Page 0 / Register 35

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
35 23 IDAC15 IDAC14 IDAC13 IDAC12 IDAC11 IDAC10 IDAC9 IDAC8
Reset Value 0 0 0 0 0 0 0 1

Table 72. Page 0 / Register 36

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
36 24 IDAC7 IDAC6 IDAC5 IDAC4 IDAC3 IDAC2 IDAC1 IDAC0
Reset Value 0 0 0 0 0 0 0 0
IDAC[15:0] IDAC (MSB)
These bits specify the number of DSP clock cycles available in one audio frame. The value should match the DSP clock FS ratio. These bits are ignored in clock auto set mode.
Default value: 0000000100000000

Table 73. Page 0 / Register 37

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
37 25 RSV IDFS IDBK IDSK IDCH IDCM DCAS IPLK
Reset Value 0 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
IDFS Ignore FS Detection
This bit controls whether to ignore the FS detection. When ignored, FS error will not cause a clock error.
Default value: 0
0: Regard FS detection
1: Ignore FS detection
IDBK Ignore BCK Detection
This bit controls whether to ignore the BCK detection against LRCK. The BCK must be stable between 32FS and 256FS inclusive or an error will be reported. When ignored, a BCK error will not cause a clock error.
Default value: 0
0: Regard BCK detection
1: Ignore BCK detection
IDSK Ignore SCK Detection
This bit controls whether to ignore the SCK detection against LRCK. Only some certain SCK ratios within some error margin are allowed. When ignored, an SCK error will not cause a clock error.
Default value: 0
0: Regard SCK detection
1: Ignore SCK detection
IDCH Ignore Clock Halt Detection
This bit controls whether to ignore the SCK halt (static or frequency is lower than acceptable) detection. When ignored an SCK halt will not cause a clock error.
Default value: 0
0: Regard SCK halt detection
1: Ignore SCK halt detection
IDCM Ignore LRCK/BCK Missing Detection
This bit controls whether to ignore the LRCK/BCK missing detection. The LRCK/BCK need to be in low state (not only static) to be deemed missing. When ignored an LRCK/BCK missing will not cause the DAC go into powerdown mode.
Default value: 0
0: Regard LRCK/BCK missing detection
1: Ignore LRCK/BCK missing detection
DCAS Disable Clock Divider Autoset
This bit enables or disables the clock auto set mode. When dealing with uncommon audio clock configuration, the auto set mode must be disabled and all clock dividers must be set manually. Addtionally, some clock detectors might also need to be disabled. The clock autoset feature will not work with PLL enabled in VCOM mode. In this case this feature has to be disabled and the clock dividers must be set manually.
Default value: 0
0: Enable clock auto set
1: Disable clock auto set
IPLK Ignore PLL Lock Detection
This bit controls whether to ignore the PLL lock detection. When ignored, PLL unlocks will not cause a clock error. The PLL lock flag at Page 0 / Register 4, bit 4 is always correct regardless of this bit.
Default value: 0
0: PLL unlocks raise clock error
1: PLL unlocks are ignored

Table 74. Page 0 / Register 40

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
40 28 RSV RSV AFMT1 AFMT0 RSV RSV ALEN1 ALEN0
Reset Value 0 0 1 0
RSV Reserved
Reserved. Do not access.
AFMT[1:0] I2S Data Format
These bits control both input and output audio interface formats for DAC operation.
Default value: 00
00: I2S
01: TDM/DSP
10: RTJ
11: LTJ
ALEN[1:0] I2S Word Length
These bits control both input and output audio interface sample word lengths for DAC operation.
Default value: 10
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits

Table 75. Page 0 / Register 41

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
41 29 AOFS7 AOFS6 AOFS5 AOFS4 AOFS3 AOFS2 AOFS1 AOFS0
Reset Value 0 0 0 0 0 0 0 0
AOFS[7:0] I2S Shift
These bits control the offset of audio data in the audio frame for both input and output. The offset is defined as the number of BCK from the starting (MSB) of audio frame to the starting of the desired audio sample.
Default value: 00000000
00000000: offset = 0 BCK (no offset)
00000001: ofsset = 1 BCK
00000010: offset = 2 BCKs
. . .
11111111: offset = 256 BCKs

Table 76. Page 0 / Register 42

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
42 2A RSV RSV AUPL1 AUPL0 RSV RSV AUPR1 AUPR0
Reset Value 0 1 0 1
RSV Reserved
Reserved. Do not access.
AUPL[1:0] Left DAC Data Path
These bits control the left channel audio data path connection.
Default value: 01
00: Zero data (mute)
01: Left channel data
10: Right channel data
11: Reserved (do not set)
AUPR[1:0] Right DAC Data Path
These bits control the right channel audio data path connection.
Default value: 01
00: Zero data (mute)
01: Right channel data
10: Left channel data
11: Reserved (do not set)

Table 77. Page 0 / Register 43

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
43 2B RSV RSV RSV PSEL4 PSEL3 PSEL2 PSEL1 PSEL0
Reset Value 0 0 0 0 1
RSV Reserved
Reserved. Do not access.
PSEL[4:0] DSP Program Selection
These bits select the DSP program to use for audio processing.
Default value: 00001
00000: Reserved (do not set)
00001: 8x/4x/2x FIR interpolation filter with de-emphasis
00010: 8x/4x/2x Low latency IIR interpolation filter with de-emphasis
00011: High attenuation x8/x4/x2 interpolation filter with de-emphasis
00100: Reserved
00101: Fixed process flow with configurable parameters
00110: Reserved (do not set)
00111: 8x Ringing-less low latency FIR interpolation filter without de-emphasis
11111:
others: Reserved (do not set)

Table 78. Page 0 / Register 44

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
44 2C RSV RSV RSV RSV RSV CMDP2 CMDP1 CMDP0
Reset Value 0 0 0
RSV Reserved
Reserved. Do not access.
CMDP[2:0] Clock Missing Detection Period
These bits set how long both BCK and LRCK keep low before the audio clocks deemed missing and the DAC transitions to powerdown mode.
Default value: 000
000: about 1 second
001: about 2 seconds
010: about 3 seconds
...
111: about 8 seconds

Table 79. Page 0 / Register 59

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
59 3B RSV AMTL2 AMTL1 AMTL0 RSV AMTR2 AMTR1 AMTR0
Reset Value 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
AMTL[2:0] Auto Mute Time for Left Channel
These bits specify the length of consecutive zero samples at left channel before the channel can be auto muted. The times shown are for 48 kHz sampling rate and will scale with other rates.
Default value: 000
000: 21 ms
001: 106 ms
010: 213 ms
011: 533 ms
100: 1.07 sec
101: 2.13 sec
110: 5.33 sec
111: 10.66 sec
AMTR[2:0] Auto Mute Time for Right Channel
These bits specify the length of consecutive zero samples at right channel before the channel can be auto muted. The times shown are for 48 kHz sampling rate and will scale with other rates.
Default value: 000
000: 21 ms
001: 106 ms
010: 213 ms
011: 533 ms
100: 1.07 sec
101: 2.13 sec
110: 5.33 sec
111: 10.66 sec

Table 80. Page 0 / Register 60

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
60 3C RSV RSV RSV RSV RSV RSV PCTL1 PCTL0
Reset Value 0 0
RSV Reserved
Reserved. Do not access.
PCTL[1:0] Digital Volume Control
These bits control the behavior of the digital volume.
Default value: 00
00: The volume for Left and right channels are independent
01: Right channel volume follows left channel setting
10: Left channel volume follows right channel setting
11: Reserved (The volume for Left and right channels are independent)

Table 81. Page 0 / Register 61

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
61 3D VOLL7 VOLL6 VOLL5 VOLL4 VOLL3 VOLL2 VOLL1 VOLL0
Reset Value 0 0 1 1 0 0 0 0
VOLL[7:0] Left Digital Volume
These bits control the left channel digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step.
Default value: 00110000
00000000: +24.0 dB
00000001: +23.5 dB
. . .
00101111: +0.5 dB
00110000: 0.0 dB
00110001: -0.5 dB
...
11111110: -103 dB
11111111: Mute

Table 82. Page 0 / Register 62

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
62 3E VOLR7 VOLR6 VOLR5 VOLR4 VOLR3 VOLR2 VOLR1 VOLR0
Reset Value 0 0 1 1 0 0 0 0
VOLR[7:0] Right Digital Volume
These bits control the right channel digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step.
Default value: 00110000
00000000: +24.0 dB
00000001: +23.5 dB
. . .
00101111: +0.5 dB
00110000: 0.0 dB
00110001: -0.5 dB
...
11111110: -103 dB
11111111: Mute

Table 83. Page 0 / Register 63

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
63 3F VNDF1 VNDF0 VNDS1 VNDS0 VNUF1 VNUF0 VNUS1 VNUS0
Reset Value 0 0 1 0 0 0 1 0
VNDF[1:0] Digital Volume Normal Ramp Down Frequency
These bits control the frequency of the digital volume updates when the volume is ramping down. The setting here is applied to soft mute request, asserted by XSMUTE pin or Page 0 / Register 3.
Default value: 00
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
VNDS[1:0] Digital Volume Normal Ramp Down Step
These bits control the step of the digital volume updates when the volume is ramping down. The setting here is applied to soft mute request, asserted by XSMUTE pin or Page 0 / Register 3.
Default value: 10
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
VNUF[1:0] Digital Volume Normal Ramp Up Frequency
These bits control the frequency of the digital volume updates when the volume is ramping up. The setting here is applied to soft unmute request, asserted by XSMUTE pin or Page 0 / Register 3.
Default value: 00
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly restore the volume (Instant unmute)
VNUS[1:0] Digital Volume Normal Ramp Up Step
These bits control the step of the digital volume updates when the volume is ramping up. The setting here is applied to soft unmute request, asserted by XSMUTE pin or Page 0 / Register 3.
Default value: 10
00: Increment by 4 dB for each update
01: Increment by 2 dB for each update
10: Increment by 1 dB for each update
11: Increment by 0.5 dB for each update

Table 84. Page 0 / Register 64

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
64 40 VEDF1 VEDF0 VEDS1 VEDS0 RSV RSV RSV RSV
Reset Value 0 0 0 0
RSV Reserved
Reserved. Do not access.
VEDF[1:0] Digital Volume Emergency Ramp Down Frequency
These bits control the frequency of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute.
Default value: 00
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
VEDS[1:0] Digital Volume Emergency Ramp Down Step
These bits control the step of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute.
Default value: 00
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update

Table 85. Page 0 / Register 65

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
65 41 RSV RSV RSV RSV RSV ACTL2 AMLE1 AMRE0
Reset Value 1 1 1
RSV Reserved
Reserved. Do not access.
ACTL[2:0] Auto Mute Control
This bit controls the behavior of the auto mute upon zero sample detection. The time length for zero detection is set with Page 0 / Register 59.
Default value: 111
0: Auto mute left channel and right channel independently.
1: Auto mute left and right channels only when both channels are about to be auto muted.
AMLE[1:0] Auto Mute Left Channel
This bit enables or disables auto mute on right channel. Note that when right channel auto mute is disabled and the Page 0 / Register 65, bit 2 is set to 1, the left channel will also never be auto muted.
Default value: 11
0: Disable right channel auto mute
1: Enable right channel auto mute
AMRE Auto Mute Right Channel
This bit enables or disables auto mute on left channel. Note that when left channel auto mute is disabled and the Page 0 / Register 65, bit 2 is set to 1, the right channel will also never be auto muted.
Default value: 1
0: Disable left channel auto mute
1: Enable left channel auto mute

Table 86. Page 0 / Register 80

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
80 50 RSV RSV RSV G1SL4 G1SL3 G1SL2 G1SL1 G1SL0
Reset Value 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
G1SL[4:0] GPIO1 Output Selection
These bits select the signal to output to GPIO1. To actually output the selected signal, the GPIO1 must be set to output mode at Page 0 / Register 8.
Default value: 00000
00000: off (low)
00001: DSP GPIO1 output
00010: Register GPIO1 output (Page 0 / Register 86, bit 0)
00011: Auto mute flag (asserted when both L and R channels are auto muted)
00100: Auto mute flag for left channel
00101: Auto mute flag for right channel
00110: Clock invalid flag (clock error or clock changing or clock missing)
00111: Serial audio interface data output (SDOUT)
01000: Analog mute flag for left channel (low active)
01001: Analog mute flag for right channel (low active)
01010: PLL lock flag
01011: Charge pump clock
01100: Reserved
01101: Reserved
01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
010000: PLL Output/4 (Requires Clock Flex Register)
OTHERS: RESERVED

Table 87. Page 0 / Register 81

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
81 51 RSV RSV RSV G2SL4 G2SL3 G2SL2 G2SL1 G2SL0
Reset Value 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
G2SL[4:0] GPIO2 Output Selection
These bits select the signal to output to GPIO2. To actually output the selected signal, the GPIO2 must be set to output mode at Page 0 / Register 8.
Default value: 00000
00000: off (low)
00001: DSP GPIO2 output
00010: Register GPIO2 output (Page 0 / Register 86, bit 1)
00011: Auto mute flag (asserted when both L and R channels are auto muted)
00100: Auto mute flag for left channel
00101: Auto mute flag for right channel
00110: Clock invalid flag (clock error or clock changing or clock missing)
00111: Serial audio interface data output (SDOUT)
01000: Analog mute flag for left channel (low active)
01001: Analog mute flag for right channel (low active)
01010: PLL lock flag
01011: Charge pump clock
01100: Reserved
01101: Reserved
01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
010000: PLL Output/4 (Requires Clock Flex Register)
OTHERS: RESERVED

Table 88. Page 0 / Register 82

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
82 52 RSV RSV RSV G3SL4 G3SL3 G3SL2 G3SL1 G3SL0
Reset Value 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
G3SL[4:0] GPIO3 Output Selection
These bits select the signal to output to GPIO3. To actually output the selected signal, the GPIO3 must be set to output mode at Page 0 / Register 8.
Default value: 00000
0000: off (low)
0001: DSP GPIO3 output
0010: Register GPIO3 output (Page 0 / Register 86, bit 2)
00011: Auto mute flag (asserted when both L and R channels are auto muted)
00100: Auto mute flag for left channel
00101: Auto mute flag for right channel
00110: Clock invalid flag (clock error or clock changing or clock missing)
00111: Serial audio interface data output (SDOUT)
01000: Analog mute flag for left channel (low active)
01001: Analog mute flag for right channel (low active)
01010: PLL lock flag
01011: Charge pump clock
01100: Reserved
01101: Reserved
01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
010000: PLL Output/4 (Requires Clock Flex Register)
OTHERS: RESERVED

Table 89. Page 0 / Register 83

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
83 53 RSV RSV RSV G4SL4 G4SL3 G4SL2 G4SL1 G4SL0
Reset Value 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
G4SL[4:0] GPIO4 Output Selection
These bits select the signal to output to GPIO4. To actually output the selected signal, the GPIO4 must be set to output mode at Page 0 / Register 8.
Default value: 00000
00000: off (low)
00001: DSP GPIO4 output
00010: Register GPIO4 output (Page 0 / Register 86, bit 3)
00011: Auto mute flag (asserted when both L and R channels are auto muted)
00100: Auto mute flag for left channel
00101: Auto mute flag for right channel
00110: Clock invalid flag (clock error or clock changing or clock missing)
00111: Serial audio interface data output (SDOUT)
01000: Analog mute flag for left channel (low active)
01001: Analog mute flag for right channel (low active)
01010: PLL lock flag
01011: Charge pump clock
01100: Reserved
01101: Reserved
01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
010000: PLL Output/4 (Requires Clock Flex Register)
OTHERS: RESERVED

Table 90. Page 0 / Register 84

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
84 54 RSV RSV RSV G5SL4 G5SL3 G5SL2 G5SL1 G5SL0
Reset Value 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
G5SL[4:0] GPIO5 Output Selection
These bits select the signal to output to GPIO5. To actually output the selected signal, the GPIO5 must be set to output mode at Page 0 / Register 8.
Default value: 00000
00000: off (low)
00001: DSP GPIO5 output
00010: Register GPIO5 output (Page 0 / Register 86, bit 4
00011: Auto mute flag (asserted when both L and R channels are auto muted)
00100: Auto mute flag for left channel
00101: Auto mute flag for right channel
00110: Clock invalid flag (clock error or clock changing or clock missing)
00111: Serial audio interface data output (SDOUT)
01000: Analog mute flag for left channel (low active)
01001: Analog mute flag for right channel (low active)
01010: PLL lock flag
01011: Charge pump clock
01100: Reserved
01101: Reserved
01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
010000: PLL Output/4 (Requires Clock Flex Register)
OTHERS: RESERVED

Table 91. Page 0 / Register 85

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
85 55 RSV RSV RSV G6SL4 G6SL3 G6SL2 G6SL1 G6SL0
Reset Value 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
G6SL[4:0] GPIO6 Output Selection
These bits select the signal to output to GPIO6. To actually output the selected signal, the GPIO6 must be set to output mode at Page 0 / Register 8.
Default value: 00000
00000: off (low)
00001: DSP GPIO6 output
00010: Register GPIO6 output (Page 0 / Register 86, bit 5)
00011: Auto mute flag (asserted when both L and R channels are auto muted)
00100: Auto mute flag for left channel
00101: Auto mute flag for right channel
00110: Clock invalid flag (clock error or clock changing or clock missing)
00111: Serial audio interface data output (SDOUT)
01000: Analog mute flag for left channel (low active)
01001: Analog mute flag for right channel (low active)
01010: PLL lock flag
01011: Charge pump clock
01100: Reserved
01101: Reserved
01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
010000: PLL Output/4 (Requires Clock Flex Register)
OTHERS: RESERVED

Table 92. Page 0 / Register 86

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
86 56 RSV RSV GOUT5 GOUT4 GOUT3 GOUT2 GOUT1 GOUT0
Reset Value 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
GOUT5 GPIO6 Output Control
This bit controls the GPIO6 output when the selection at Page 0 / Register 85 is set to 0010 (register output)
Default value: 0
0: Output low
1: Output high
GOUT4 GPIO5 Output Control
This bit controls the GPIO5 output when the selection at Page 0 / Register 84 is set to 0010 (register output)
Default value: 0
0: Output low
1: Output high
GOUT3 GPIO4 Output Control
This bit controls the GPIO4 output when the selection at Page 0 / Register 83 is set to 0010 (register output)
Default value: 0
0: Output low
1: Output high
GOUT2 GPIO3 Output Control
This bit controls the GPIO3 output when the selection at Page 0 / Register 82 is set to 0010 (register output)
Default value: 0
0: Output low
1: Output high
GOUT1 GPIO2 Output Control
This bit controls the GPIO2 output when the selection at Page 0 / Register 81 is set to 0010 (register output)
Default value: 0
0: Output low
1: Output high
GOUT0 GPIO1 Output Control
This bit controls the GPIO1 output when the selection at Page 0 / Register 80 is set to 0010 (register output)
Default value: 0
0: Output low
1: Output high

Table 93. Page 0 / Register 87

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
87 57 RSV RSV GINV5 GINV4 GINV3 GINV2 GINV1 GINV0
Reset Value 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
GINV5 GPIO6 Output Inversion
This bit controls the polarity of GPIO6 output. When set to 1, the output will be inverted for any signal being selected.
Default value: 0
0: Non-inverted
1: Inverted
GINV4 GPIO5 Output Inversion
This bit controls the polarity of GPIO5 output. When set to 1, the output will be inverted for any signal being selected.
Default value: 0
0: Non-inverted
1: Inverted
GINV3 GPIO4 Output Inversion
This bit controls the polarity of GPIO4 output. When set to 1, the output will be inverted for any signal being selected.
Default value: 0
0: Non-inverted
1: Inverted
GINV2 GPIO3 Output Inversion
This bit controls the polarity of GPIO3 output. When set to 1, the output will be inverted for any signal being selected.
Default value: 0
0: Non-inverted
1: Inverted
GINV1 GPIO2 Output Inversion
This bit controls the polarity of GPIO2 output. When set to 1, the output will be inverted for any signal being selected.
Default value: 0
0: Non-inverted
1: Inverted
GINV0 GPIO1 Output Inversion
This bit controls the polarity of GPIO1 output. When set to 1, the output will be inverted for any signal being selected.
Default value: 0
0: Non-inverted
1: Inverted

Table 94. Page 0 / Register 90

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
90 5A RSV RSV RSV L1OV R1OV L2OV R2OV SFOV
Reset Value
RSV Reserved
Reserved. Do not access.
L1OV Left1 Overflow (Read Only)
This bit indicates whether the left channel of DSP first output port has overflow. This bit is sticky and is cleared when read.
0: No overflow
1: Overflow occurred
R1OV Right1 Overflow (Read Only)
The bit indicates whether the right channel of DSP first output port has overflow. This bit is sticky and is cleared when read.
0: No overflow
1: Overflow occurred
L2OV Left2 Overflow (Read Only)
This bit indicates whether the left channel of DSP second output port has overflow. This bit is sticky and is cleared when read.
0: No overflow
1: Overflow occurred
R2OV Right2 Overflow (Read Only)
The bit indicates whether the right channel of DSP second output port has overflow. This bit is sticky and is cleared when read.
0: No overflow
1: Overflow occurred
SFOV Shifter Overflow (Read Only)
This bit indicates whether overflow occurred in the DSP shifter (possible sample corruption). This bit is sticky and is cleared when read.
0: No overflow
1: Overflow occurred

Table 95. Page 0 / Register 91

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
91 5B RSV DTFS2 DTFS1 DTFS0 DTSR3 DTSR2 DTSR1 DTSR0
Reset Value
RSV Reserved
Reserved. Do not access.
DTFS[2:0] Detected FS (Read Only)
These bits indicate the currently detected audio sampling rate.
000: Error (Out of valid range)
001: 8 kHz
010: 16 kHz
011: 32-48 kHz
100: 88.2-96 kHz
101: 176.4-192 kHz
110: 384 kHz
DTSR[3:0] Detected SCK Ratio (Read Only)
These bits indicate the currently detected SCK ratio. Note that even if the SCK ratio is not indicated as error, clock error might still be flagged due to incompatible combination with the sampling rate. Specifically the SCK ratio must be high enough to allow enough DSP cycles for minimal audio processing when PLL is disabled. The absolute SCK frequency must also be lower than 50 MHz.
0000: Ratio error (The SCK ratio is not allowed)
0001: SCK = 32 FS
0010: SCK = 48 FS
0011: SCK = 64 FS
0100: SCK = 128 FS
0101: SCK = 192 FS
0110: SCK = 256 FS
0111: SCK = 384 FS
1000: SCK = 512 FS
1001: SCK = 768 FS
1010: SCK = 1024 FS
1011: SCK = 1152 FS
1100: SCK = 1536 FS
1101: SCK = 2048 FS
1110: SCK = 3072 FS

Table 96. Page 0 / Register 92

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
92 5C RSV RSV RSV RSV RSV RSV RSV DTBR8
Reset Value

Table 97. Page 0 / Register 93

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
93 5D DTBR7 DTBR6 DTBR5 DTBR4 DTBR3 DTBR2 DTBR1 DTBR0
Reset Value
RSV Reserved
Reserved. Do not access.
DTBR[8:0] Detected BCK Ratio (MSB) (Read Only)
These bits indicate the currently detected BCK ratio, that is, the number of BCK clocks in one audio frame. Note that for extreme case of BCK = 1 FS (which is not usable anyway), the detected ratio will be unreliable.

Table 98. Page 0 / Register 94

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
94 5E RSV CDST PLL-L LrckBck fS-SCKr SCKval BCKval fSval
Reset Value
RSV Reserved
Reserved. Do not access.
CDST Clock Detector Status (Read Only)
This bit indicates whether the SCK clock is present or not.
0: SCK is present
1: SCK is missing (halted)
PLL-L PLL locked (Read Only)
This bit indicates whether the PLL is locked or not. The PLL will be reported as unlocked when it is disabled.
0: PLL is locked
1: PLL is unlocked
LrckBck LRCK-BCK present (Read Only)
This bit indicates whether the both LRCK and BCK are missing (tied low) or not.
0: LRCK and/or BCK is present
1: LRCK and BCK are missing
fS-SCKr Sample rate SCK ratio valid (Read Only)
This bit indicates whether the combination of current sampling rate and SCK ratio is valid for clock auto set.
0: The combination of FS/SCK ratio is valid
1: Error (clock auto set is not possible)
SCKval SCK valid (Read Only)
This bit indicates whether the SCK is valid or not. The SCK ratio must be detectable to be valid. There is a limitation with this flag, that is, when the low period of LRCK is less than or equal to 5 BCKs, this flag will be asserted (SCK invalid reported).
0: SCK is valid
1: SCK is invalid
BCKval BCK valid (Read Only)
This bit indicates whether the BCK is valid or not. The BCK ratio must be stable and in the range of 32-256FS to be valid.
0: BCK is valid
1: BCK is invalid
fSval fS valid (Read Only)
This bit indicated whether the audio sampling rate is valid or not. The sampling rate must be detectable to be valid. There is a limitation with this flag, that is when this flag is asserted and Page 0 / Register 37 is set to ignore all asserted error flags such that the DAC recovers, this flag will be de-asserted (sampling rate invalid not reported anymore).
0: Sampling rate is valid
1: Sampling rate is invalid

Table 99. Page 0 / Register 95

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
95 5F RSV RSV RSV LTSH RSV CKMF CSRF CERF
Reset Value
RSV Reserved
Reserved. Do not access.
LTSH Latched Clock Halt (Read Only)
This bit indicates whether SCK halt has occurred. The bit is cleared when read.
0: SCK halt has not occurred
1: SCK halt has occurred since last read
CKMF Clock Missing (Read Only)
This bit indicates whether the LRCK and BCK are missing (tied low).
0: LRCK and/or BCK is present
1: LRCK and BCK are missing
CSRF Clock Resync Request (Read Only)
This bit indicates whether the clock resynchronization is in progress.
0: Not resynchronizing
1: Clock resynchronization is in progress
CERF Clock Error (Read Only)
This bit indicates whether a clock error is being reported.
0: Clock is valid
1: Clock is invalid (Error)

Table 100. Page 0 / Register 108

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
108 6C RSV RSV RSV RSV RSV RSV AMLM AMRM
Reset Value
RSV Reserved
Reserved. Do not access.
AMLM Left Analog Mute Monitor (Read Only)
This bit is a monitor for left channel analog mute status.
0: Mute
1: Unmute
AMRM Right Analog Mute Monitor (Read Only)
This bit is a monitor for right channel analog mute status.
0: Mute
1: Unmute

Table 101. Page 0 / Register 109

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
109 6D RSV RSV RSV SDTM RSV RSV RSV SHTM
Reset Value
RSV Reserved
Reserved. Do not access.
SDTM Short detect monitor (Read Only)
This bit indicates whether line output short is occuring.
0: Normal (No short)
1: Line output is being shorted
SHTM Short detected monitor (Read Only)
This bit indicates whether line output short has occurred since last read. This bit is sticky and is cleared when read.
0: No short
1: Line output short occurred

Table 102. Page 0 / Register 114

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
114 72 RSV RSV RSV RSV RSV RSV MTST1 MTST0
Reset Value
RSV Reserved
Reserved. Do not access.
MTST[1:0] MUTEZ status (Read Only)
These bits indicate the output of the XSMUTE level decoder for monitoring purpose.
11: 0.7 VDD ≤ XSMUTE
01: 0.3 VDD ≤ XSMUTE < 0.7 VDD
00: 0.3 VDD > XSMUTE

Table 103. Page 0 / Register 115

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
115 73 RSV RSV RSV RSV RSV RSV FSMM1 FSMM0
Reset Value
RSV Reserved
Reserved. Do not access.
FSMM[1:0] FS Speed Mode Monitor (Read Only)
These bits indicate the actual FS operation mode being used. The actual value is the auto set one when clock auto set is active and register set one when clock auto set is disabled.
00: Single speed (FS ≤ 48 kHz)
01: Double speed (48 kHz < FS ≤ 96 kHz)
10: Quad speed (96 kHz < FS ≤ 192 kHz)
11: Octal speed (192 kHz < FS ≤ 384 kHz)

Table 104. Page 0 / Register 118

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
118 76 BOTM RSV RSV RSV PSTM3 PSTM2 PSTM1 PSTM0
Reset Value
RSV Reserved
Reserved. Do not access.
BOTM DSP Boot Done Flag (Read Only)
This bit indicates whether the DSP boot is completed.
0: DSP is booting
1: DSP boot completed
PSTM[3:0] Power State (Read Only)
These bits indicate the current power state of the DAC.
0000: Powerdown
0001: Wait for CP voltage valid
0010: Calibration
0011: Calibration
0100: Volume ramp up
0101: Run (Playing)
0110: Line output short / Low impedance
0111: Volume ramp down
1000: Standby

Table 105. Page 0 / Register 119

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
119 77 RSV RSV GPIN5 GPIN4 GPIN3 GPIN2 GPIN1 RSV
Reset Value
RSV Reserved
Reserved. Do not access.
GPIN[5:0] GPIO Input States (Read Only)
This bit indicates the logic level at GPIO6 pin.
0: Low
1: High

Table 106. Page 0 / Register 120

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
120 78 RSV RSV RSV AMFL RSV RSV RSV AMFR
Reset Value
RSV Reserved
Reserved. Do not access.
AMFL Auto Mute Flag for Left Channel (Read Only)
This bit indicates the auto mute status for left channel.
0: Not auto muted
1: Auto muted
AMFR Auto Mute Flag for Right Channel (Read Only)
This bit indicates the auto mute status for right channel.
0: Not auto muted
1: Auto muted

Table 107. Page 0 / Register 121

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
121 79 RSV RSV RSV RSV RSV RSV RSV DAMD
Reset Value 0
RSV Reserved
Reserved. Do not access.
DAMD DAC Mode
This bit controls the DAC architecture to vary the DAC auditory signature.
Default value: 0
0: Mode1 - New hyper-advanced current-segment architecture
1: Mode2 - Classic PCM1792 advanced current-segment architecture

Table 108. Page 0 / Register 122

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
122 7A RSV RSV RSV RSV RSV RSV RSV EIFM
Reset Value 0
RSV Reserved
Reserved. Do not access.
EIFM External Interpolation Filter Mode
This bit enables or disables the PCM1792 External Interpolation Filter Mode. This mode is used with a PCM1792 in external digital filter mode.
Default value: 0
0: Normal mode
1: External Interpolation Filter Mode

Table 109. Page 0 / Register 123

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
123 7B RSV G1MC2 G1MC1 G1MC0 RSV G2MC2 G2MC1 G2MC0
Reset Value 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
G1MC[2:0] GPIO1 output for External Interpolation Filter Mode
These bits select a signal to be output to GPIO1 in External Interpolation Filter mode.
Default value: 000
000: Logic low
001: MS
010: BCK (256FS)
011: WDCK (8FS)
100: DATAL
101: DATAR
110: Raw DIN (from DIN pin)
111: Raw LRCK (from LRCK pin)
G2MC[2:0] GPIO2 output for External Interpolation Filter Mode
These bits select a signal to be output to GPIO2 in External Interpolation Filter mode.
Default value: 000
000: Logic low
001: MS
010: BCK (256FS)
011: WDCK (8FS)
100: DATAL
101: DATAR
110: Raw DIN (from DIN pin)
111: Raw LRCK (from LRCK pin)

Table 110. Page 0 / Register 124

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
124 7C RSV G3MC2 G3MC1 G3MC0 RSV G4MC2 G4MC1 G4MC0
Reset Value 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
G3MC[2:0] GPIO3 output for External Interpolation Filter Mode
These bits select a signal to be output to GPIO3 in External Interpolation Filter Mode.
Default value: 000
000: Logic low
001: MS
010: BCK (256FS)
011: WDCK (8FS)
100: DATAL
101: DATAR
110: Raw DIN (from DIN pin)
111: Raw LRCK (from LRCK pin)
G4MC[2:0] GPIO4 output for External Interpolation Filter Mode
These bits select a signal to be output to GPIO4 in External Interpolation Filter Mode.
Default value: 000
000: Logic low
001: MS
010: BCK (256FS)
011: WDCK (8FS)
100: DATAL
101: DATAR
110: Raw DIN (from DIN pin)
111: Raw LRCK (from LRCK pin)

Table 111. Page 0 / Register 125

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
125 7D RSV G5MC2 G5MC1 G5MC0 RSV G6MC2 G6MC1 G6MC0
Reset Value 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
G5MC[2:0] GPIO5 output for External Interpolation Filter Mode
These bits select a signal to be output to GPIO5 in External Interpolation Filter mode.
Default value: 000
000: Logic low
001: MS
010: BCK (256FS)
011: WDCK (8FS)
100: DATAL
101: DATAR
110: Raw DIN (from DIN pin)
111: Raw LRCK (from LRCK pin)
G6MC[2:0] GPIO6 output for External Interpolation Filter Mode
These bits select a signal to be output to GPIO6 in External Interpolation Filter mode.
Default value: 000
000: Logic low
001: MS
010: BCK (256FS)
011: WDCK (8FS)
100: DATAL
101: DATAR
110: Raw DIN (from DIN pin)
111: Raw LRCK (from LRCK pin)

13.1.1.3 Page 1 Registers

Table 112. Page 1 / Register 1

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
1 01 RSV RSV RSV RSV RSV RSV RSV OSEL
Reset Value 0
RSV Reserved
Reserved. Do not access.
OSEL Output Amplitude Type
This bit selects the output amplitude type. The clock autoset feature will not work with PLL enabled in VCOM mode. In this case this feature has to be disabled via Page 0 / Register 37 and the clock dividers must be set manually.
Default value: 0
0: VREF mode (Constant output amplitude against AVDD variation)
1: VCOM mode (Output amplitude is proportional to AVDD variation)

Table 113. Page 1 / Register 2

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
2 02 RSV RSV RSV LAGN RSV RSV RSV RAGN
Reset Value 0 0
RSV Reserved
Reserved. Do not access.
LAGN Analog Gain Control for Left Channel
This bit controls the left channel analog gain.
Default value: 0
0: 0 dB
1:-6 dB
RAGN Analog Gain Control for Right Channel
This bit controls the right channel analog gain.
Default value: 0
0: 0 dB
1: -6 dB

Table 114. Page 1 / Register 5

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
5 05 RSV RSV RSV RSV RSV RSV UEPD UIPD
Reset Value 0 0
RSV Reserved
Reserved. Do not access.
UEPD External UVP Control
This bit enables or disables detection of power supply drop via XSMUTE pin (External Under Voltage Protection).
Default value: 0
0: Enabled
1: Disabled
UIPD Internal UVP Control
This bit enables or disables internal detection of AVDD voltage drop (Internal Under Voltage Protection).
Default value: 0
0: Enabled
1: Disabled

Table 115. Page 1 / Register 6

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
6 06 RSV RSV RSV RSV RSV RSV RSV AMCT
Reset Value 0
RSV Reserved
Reserved. Do not access.
AMCT Analog Mute Control
This bit enables or disables analog mute following digital mute.
Default value: 0
0: Enabled
1: Disabled

Table 116. Page 1 / Register 7

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
7 07 RSV RSV RSV AGBL RSV RSV RSV AGBR
Reset Value 0 0
RSV Reserved
Reserved. Do not access.
AGBL Analog +10% Gain for Left Channel
This bit enables or disables amplitude boost mode for left channel.
Default value: 0
0: Normal amplitude
1: +10% (+0.8 dB) boosted amplitude
AGBR Analog +10% Gain for Right Channel
This bit enables or disables amplitude boost mode for right channel.
Default value: 0
0: Normal amplitude
1: +10% (+0.8 dB) boosted amplitude

Table 117. Page 1 / Register 8

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
8 08 RSV RSV RSV RSV RSV RSV RSV RCMF
Reset Value 0
RSV Reserved
Reserved. Do not access.
RCMF VCOM Reference Ramp Up
This bit controls the VCOM voltage ramp up speed.
Default value: 0
0: Normal ramp up, ~600ms with external capacitance = 1uF
1: Fast ramp up, ~3ms with external capacitance = 1uF

Table 118. Page 1 / Register 9

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
9 09 RSV RSV RSV RSV RSV RSV RSV VCPD
Reset Value 1
RSV Reserved
Reserved. Do not access.
VCPD Power down control for VCOM
This bit controls VCOM powerdown switch.
Default value: 1
0: VCOM is powered on
1: VCOM is powered down

13.1.1.4 Page 44 Registers

Table 119. Page 44 / Register 1

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
1 01 RSV RSV RSV RSV ACRM AMDC ACRS ACSW
Reset Value 0 0
RSV Reserved
Reserved. Do not access.
ACRM Active CRAM Monitor (Read Only)
This bit indicates which CRAM is being accessed by the DSP when adaptive mode is disabled. When adaptive mode is enabled, this bit has no meaning.
0: CRAM A is being used by the DSP
1: CRAM B is being used by the DSP
AMDC Adaptive Mode Control
This bit controls the DSP adaptive mode. When in adaptive mode, only CRAM A is accessible via serial interface when the DSP is disabled (DAC in standby state), while when the DSP is enabled (DAC is run state) the CRAM A can only be accessed by the DSP and the CRAM B can only be accessed by the serial interface, or vice versa depending on the value of CRAMSTAT. When not in adaptive mode, both CRAM A and B can be accessed by the serial interface when the DSP is disabled, but when the DSP is enabled, no CRAM can be accessed by serial interface. The DSP can access either CRAM, which can be monitored at SWPMON.
Default value: 0
0: Adaptive mode disabled
1: Adaptive mode enabled
ACRS Active CRAM Selection (Read Only)
This bit indicates which CRAM currently serves as the active one. The other CRAM serves as an update buffer, and can accessed by serial interface (SPI/I2C)
0: CRAM A is active and being used by the DSP
1: CRAM B is active and being used by the DSP
ACSW Switch Active CRAM
This bit is used to request switching roles of the two buffers, that is, switching the active buffer role between CRAM A and CRAM B. This bit is cleared automatically when the switching process completed.
Default value: 0
0: No switching requested or switching completed
1: Switching is being requested

13.1.1.5 Page 253 Registers

Table 120. Page 253 / Register 63

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
63 3F PLLFLEX17 PLLFLEX16 PLLFLEX15 PLLFLEX14 PLLFLEX13 PLLFLEX12 PLLFLEX11 PLLFLEX10
Reset Value 0 0 0 0 0 0 0 0
PLLFLEX1[7:0] Clock Flex Register #1
Clock Flex Register #1. Write 0x11 to this register to allow advanced clock tree functions. See Clocking Overview section.
Default value: 00000000

Table 121. Page 253 / Register 64

Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
64 40 PLLFLEX27 PLLFLEX26 PLLFLEX25 PLLFLEX24 PLLFLEX23 PLLFLEX22 PLLFLEX21 PLLFLEX20
Reset Value 0 0 0 0 0 0 0 0
PLLFLEX2[7:0] Clock Flex Register #2
Clock Flex Register #2. Write 0xFF to this register to allow advanced clock tree functions. See Clocking Overview section.
Default value: 00000000

13.1.2 PLL Tables for Software Controlled Devices

Table 122. Recommended Clock Divider Settings for PLL as Master Clock (VREF Mode)

fS (kHz) RSCK SCK (MHz) PLL VCO (MHz) P PLL REF (MHz) M = K*R K = J.D R PLL fS DSP fS NMAC DSP CLK (MHz) MOD fS MOD F (kHz) NDAC DOSR % ERROR NCP CP F (kHz)
8 128 1.024 98.304 1 1.024 96 48 2 12288 1024 12 8.192 768 6144 16 48 0 4 1536
8 192 1.536 98.304 1 1.536 64 32 2 12288 1024 12 8.192 768 6144 16 48 0 4 1536
8 256 2.048 98.304 1 2.048 48 48 1 12288 1024 12 8.192 768 6144 16 48 0 4 1536
8 384 3.072 98.304 3 1.024 96 48 2 12288 1024 12 8.192 768 6144 16 48 0 4 1536
8 512 4.096 98.304 3 1.365 72 36 2 12288 1024 12 8.192 768 6144 16 48 0 4 1536
8 768 6.144 98.304 3 2.048 48 48 1 12288 1024 12 8.192 768 6144 16 48 0 4 1536
8 1024 8.192 98.304 3 2.731 36 36 1 12288 1024 12 8.192 768 6144 16 48 0 4 1536
8 1152 9.216 98.304 9 1.024 96 48 2 12288 1024 12 8.192 768 6144 16 48 0 4 1536
8 1536 12.288 98.304 9 1.365 72 36 2 12288 1024 12 8.192 768 6144 16 48 0 4 1536
8 2048 16.384 98.304 9 1.82 54 54 1 12288 1024 12 8.192 768 6144 16 48 0 4 1536
8 3072 24.576 98.304 9 2.731 36 36 1 12288 1024 12 8.192 768 6144 16 48 0 4 1536
11.025 128 1.4112 90.3168 1 1.411 64 32 2 8192 1024 8 11.2896 512 5644.8 16 32 0 4 1411.2
11.025 192 2.1168 90.3168 3 0.706 128 32 4 8192 1024 8 11.2896 512 5644.8 16 32 0 4 1411.2
11.025 256 2.8224 90.3168 1 2.822 32 32 1 8192 1024 8 11.2896 512 5644.8 16 32 0 4 1411.2
11.025 384 4.2336 90.3168 3 1.411 64 32 2 8192 1024 8 11.2896 512 5644.8 16 32 0 4 1411.2
11.025 512 5.6448 90.3168 3 1.882 48 48 1 8192 1024 8 11.2896 512 5644.8 16 32 0 4 1411.2
11.025 768 8.4672 90.3168 3 2.822 32 32 1 8192 1024 8 11.2896 512 5644.8 16 32 0 4 1411.2
11.025 1024 11.2896 90.3168 3 3.763 24 24 1 8192 1024 8 11.2896 512 5644.8 16 32 0 4 1411.2
11.025 1152 12.7008 90.3168 9 1.411 64 32 2 8192 1024 8 11.2896 512 5644.8 16 32 0 4 1411.2
11.025 1536 16.9344 90.3168 9 1.882 48 48 1 8192 1024 8 11.2896 512 5644.8 16 32 0 4 1411.2
11.025 2048 22.5792 90.3168 9 2.509 36 36 1 8192 1024 8 11.2896 512 5644.8 16 32 0 4 1411.2
11.025 3072 33.8688 90.3168 9 3.763 24 24 1 8192 1024 8 11.2896 512 5644.8 16 32 0 4 1411.2
16 64 1.024 98.304 1 1.024 96 48 2 6144 1024 6 16.384 384 6144 16 24 0 4 1536
16 128 2.048 98.304 1 2.048 48 48 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536
16 192 3.072 98.304 1 3.072 32 32 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536
16 256 4.096 98.304 1 4.096 24 24 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536
16 384 6.144 98.304 3 2.048 48 48 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536
16 512 8.192 98.304 3 2.731 36 36 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536
16 768 12.288 98.304 3 4.096 24 24 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536
16 1024 16.384 98.304 3 5.461 18 18 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536
16 1152 18.432 98.304 3 6.144 16 16 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536
16 1536 24.576 98.304 9 2.731 36 36 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536
16 2048 32.768 98.304 9 3.641 27 27 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536
16 3072 49.152 98.304 9 5.461 18 18 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536
22.05 64 1.4112 90.3168 1 1.411 64 32 2 4096 1024 4 22.5792 256 5644.8 16 16 0 4 1411.2
22.05 128 2.8224 90.3168 1 2.822 32 32 1 4096 1024 4 22.5792 256 5644.8 16 16 0 4 1411.2
22.05 192 4.2336 90.3168 3 1.411 64 32 2 4096 1024 4 22.5792 256 5644.8 16 16 0 4 1411.2
22.05 256 5.6448 90.3168 1 5.645 16 16 1 4096 1024 4 22.5792 256 5644.8 16 16 0 4 1411.2
22.05 384 8.4672 90.3168 3 2.822 32 32 1 4096 1024 4 22.5792 256 5644.8 16 16 0 4 1411.2
22.05 512 11.2896 90.3168 3 3.763 24 24 1 4096 1024 4 22.5792 256 5644.8 16 16 0 4 1411.2
22.05 768 16.9344 90.3168 3 5.645 16 16 1 4096 1024 4 22.5792 256 5644.8 16 16 0 4 1411.2
22.05 1024 22.5792 90.3168 3 7.526 12 12 1 4096 1024 4 22.5792 256 5644.8 16 16 0 4 1411.2
22.05 1152 25.4016 90.3168 9 2.822 32 32 1 4096 1024 4 22.5792 256 5644.8 16 16 0 4 1411.2
22.05 1536 33.8688 90.3168 9 3.763 24 24 1 4096 1024 4 22.5792 256 5644.8 16 16 0 4 1411.2
22.05 2048 45.1584 90.3168 9 5.018 18 18 1 4096 1024 4 22.5792 256 5644.8 16 16 0 4 1411.2
32 32 1.024 98.304 1 1.024 96 48 2 3072 1024 3 32.768 192 6144 16 12 0 4 1536
32 48 1.536 98.304 1 1.536 64 16 4 3072 1024 3 32.768 192 6144 16 12 0 4 1536
32 64 2.048 98.304 1 2.048 48 24 2 3072 1024 3 32.768 192 6144 16 12 0 4 1536
32 128 4.096 98.304 1 4.096 24 24 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536
32 192 6.144 98.304 3 2.048 48 48 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536
32 256 8.192 98.304 2 4.096 24 24 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536
32 384 12.288 98.304 3 4.096 24 24 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536
32 512 16.384 98.304 3 5.461 18 18 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536
32 768 24.576 98.304 3 8.192 12 12 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536
32 1024 32.768 98.304 3 10.923 9 9 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536
32 1152 36.864 98.304 9 4.096 24 24 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536
32 1536 49.152 98.304 6 8.192 12 12 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536
44.1 32 1.4112 90.3168 1 1.411 64 32 2 2048 1024 2 45.1584 128 5644.8 16 8 0 4 1411.2
44.1 64 2.8224 90.3168 1 2.822 32 16 2 2048 1024 2 45.1584 128 5644.8 16 8 0 4 1411.2
44.1 128 5.6448 90.3168 1 5.645 16 16 1 2048 1024 2 45.1584 128 5644.8 16 8 0 4 1411.2
44.1 192 8.4672 90.3168 3 2.822 32 32 1 2048 1024 2 45.1584 128 5644.8 16 8 0 4 1411.2
44.1 256 11.2896 90.3168 2 5.645 16 16 1 2048 1024 2 45.1584 128 5644.8 16 8 0 4 1411.2
44.1 384 16.9344 90.3168 3 5.645 16 16 1 2048 1024 2 45.1584 128 5644.8 16 8 0 4 1411.2
44.1 512 22.5792 90.3168 3 7.526 12 12 1 2048 1024 2 45.1584 128 5644.8 16 8 0 4 1411.2
44.1 768 33.8688 90.3168 3 11.29 8 8 1 2048 1024 2 45.1584 128 5644.8 16 8 0 4 1411.2
44.1 1024 45.1584 90.3168 3 15.053 6 6 1 2048 1024 2 45.1584 128 5644.8 16 8 0 4 1411.2
48 32 1.536 98.304 1 1.536 64 32 2 2048 1024 2 49.152 128 6144 16 8 0 4 1536
48 64 3.072 98.304 1 3.072 32 16 2 2048 1024 2 49.152 128 6144 16 8 0 4 1536
48 128 6.144 98.304 1 6.144 16 16 1 2048 1024 2 49.152 128 6144 16 8 0 4 1536
48 192 9.216 98.304 3 3.072 32 32 1 2048 1024 2 49.152 128 6144 16 8 0 4 1536
48 256 12.288 98.304 2 6.144 16 16 1 2048 1024 2 49.152 128 6144 16 8 0 4 1536
48 384 18.432 98.304 3 6.144 16 16 1 2048 1024 2 49.152 128 6144 16 8 0 4 1536
48 512 24.576 98.304 3 8.192 12 12 1 2048 1024 2 49.152 128 6144 16 8 0 4 1536
48 768 36.864 98.304 3 12.288 8 8 1 2048 1024 2 49.152 128 6144 16 8 0 4 1536
48 1024 49.152 98.304 3 16.384 6 6 1 2048 1024 2 49.152 128 6144 16 8 0 4 1536
96 32 3.072 98.304 1 3.072 32 16 2 1024 512 2 49.152 64 6144 16 4 0 4 1536
96 48 4.608 98.304 3 1.536 64 32 2 1024 512 2 49.152 64 6144 16 4 0 4 1536
96 64 6.144 98.304 1 6.144 16 8 2 1024 512 2 49.152 64 6144 16 4 0 4 1536
96 128 12.288 98.304 2 6.144 16 16 1 1024 512 2 49.152 64 6144 16 4 0 4 1536
96 192 18.432 98.304 3 6.144 16 16 1 1024 512 2 49.152 64 6144 16 4 0 4 1536
96 256 24.576 98.304 4 6.144 16 16 1 1024 512 2 49.152 64 6144 16 4 0 4 1536
96 384 36.864 98.304 6 6.144 16 16 1 1024 512 2 49.152 64 6144 16 4 0 4 1536
96 512 49.152 98.304 8 6.144 16 16 1 1024 512 2 49.152 64 6144 16 4 0 4 1536
192 32 6.144 98.304 1 6.144 16 8 2 512 256 2 49.152 32 6144 16 2 0 4 1536
192 48 9.216 98.304 3 3.072 32 16 2 512 256 2 49.152 32 6144 16 2 0 4 1536
192 64 12.288 98.304 1 12.288 8 4 2 512 256 2 49.152 32 6144 16 2 0 4 1536
192 128 24.576 98.304 2 12.288 8 8 1 512 256 2 49.152 32 6144 16 2 0 4 1536
192 192 36.864 98.304 3 12.288 8 8 1 512 256 2 49.152 32 6144 16 2 0 4 1536
192 256 49.152 98.304 4 12.288 8 8 1 512 256 2 49.152 32 6144 16 2 0 4 1536
384 32 12.288 98.304 2 6.144 16 8 2 256 128 2 49.152 16 6144 16 1 0 4 1536
384 48 18.432 98.304 3 6.144 16 8 2 256 128 2 49.152 16 6144 16 1 0 4 1536
384 64 24.576 98.304 2 12.288 8 4 2 256 128 2 49.152 16 6144 16 1 0 4 1536
384 128 49.152 98.304 4 12.288 8 8 1 256 128 2 49.152 16 6144 16 1 0 4 1536

Table 123. Recommended Clock Divider Settings for PLL as Master Clock (VCOM Mode)

fS (kHz) RSCK SCK (MHz) PLL VCO (MHz) P PLL REF (MHz) M = K*R K = J.D R PLL fS DSP fS NMAC DSP CLK (MHz) MOD fS MOD F (kHz) NDAC DOSR % ERROR NCP CP F (kHz)
8 128 1.024 73.728 1 1.024 72 36 2 9216 768 12 6.144 768 6144 12 48 0 4 1536
8 192 1.536 73.728 1 1.536 48 24 2 9216 768 12 6.144 768 6144 12 48 0 4 1536
8 256 2.048 73.728 1 2.048 36 36 1 9216 768 12 6.144 768 6144 12 48 0 4 1536
8 384 3.072 73.728 1 3.072 24 12 2 9216 768 12 6.144 768 6144 12 48 0 4 1536
8 512 4.096 73.728 2 2.048 36 36 1 9216 768 12 6.144 768 6144 12 48 0 4 1536
8 768 6.144 73.728 3 2.048 36 36 1 9216 768 12 6.144 768 6144 12 48 0 4 1536
8 1024 8.192 73.728 4 2.048 36 36 1 9216 768 12 6.144 768 6144 12 48 0 4 1536
8 1152 9.216 73.728 6 1.536 48 48 1 9216 768 12 6.144 768 6144 12 48 0 4 1536
8 1536 12.288 73.728 6 2.048 36 36 1 9216 768 12 6.144 768 6144 12 48 0 4 1536
8 2048 16.384 73.728 8 2.048 36 36 1 9216 768 12 6.144 768 6144 12 48 0 4 1536
8 3072 24.576 73.728 12 2.048 36 36 1 9216 768 12 6.144 768 6144 12 48 0 4 1536
11.025 128 1.4112 84.672 1 1.411 60 30 2 7680 960 8 10.584 512 5644.8 15 32 0 4 1411.2
11.025 192 2.1168 84.672 1 2.117 40 10 4 7680 960 8 10.584 512 5644.8 15 32 0 4 1411.2
11.025 256 2.8224 84.672 1 2.822 30 30 1 7680 960 8 10.584 512 5644.8 15 32 0 4 1411.2
11.025 384 4.2336 84.672 2 2.117 40 20 2 7680 960 8 10.584 512 5644.8 15 32 0 4 1411.2
11.025 512 5.6448 84.672 2 2.822 30 30 1 7680 960 8 10.584 512 5644.8 15 32 0 4 1411.2
11.025 768 8.4672 84.672 3 2.822 30 30 1 7680 960 8 10.584 512 5644.8 15 32 0 4 1411.2
11.025 1024 11.2896 84.672 4 2.822 30 30 1 7680 960 8 10.584 512 5644.8 15 32 0 4 1411.2
11.025 1152 12.7008 84.672 6 2.117 40 20 2 7680 960 8 10.584 512 5644.8 15 32 0 4 1411.2
11.025 1536 16.9344 84.672 8 2.117 40 40 1 7680 960 8 10.584 512 5644.8 15 32 0 4 1411.2
11.025 2048 22.5792 84.672 8 2.822 30 30 1 7680 960 8 10.584 512 5644.8 15 32 0 4 1411.2
11.025 3072 33.8688 84.672 8 4.234 20 20 1 7680 960 8 10.584 512 5644.8 15 32 0 4 1411.2
16 64 1.024 73.728 1 1.024 72 36 2 4608 768 6 12.288 384 6144 12 24 0 4 1536
16 128 2.048 73.728 1 2.048 36 36 1 4608 768 6 12.288 384 6144 12 24 0 4 1536
16 192 3.072 73.728 1 3.072 24 24 1 4608 768 6 12.288 384 6144 12 24 0 4 1536
16 256 4.096 73.728 2 2.048 36 36 1 4608 768 6 12.288 384 6144 12 24 0 4 1536
16 384 6.144 73.728 3 2.048 36 36 1 4608 768 6 12.288 384 6144 12 24 0 4 1536
16 512 8.192 73.728 4 2.048 36 36 1 4608 768 6 12.288 384 6144 12 24 0 4 1536
16 768 12.288 73.728 6 2.048 36 36 1 4608 768 6 12.288 384 6144 12 24 0 4 1536
16 1024 16.384 73.728 8 2.048 36 36 1 4608 768 6 12.288 384 6144 12 24 0 4 1536
16 1152 18.432 73.728 9 2.048 36 36 1 4608 768 6 12.288 384 6144 12 24 0 4 1536
16 1536 24.576 73.728 8 3.072 24 24 1 4608 768 6 12.288 384 6144 12 24 0 4 1536
16 2048 32.768 73.728 8 4.096 18 18 1 4608 768 6 12.288 384 6144 12 24 0 4 1536
16 3072 49.152 73.728 8 6.144 12 12 1 4608 768 6 12.288 384 6144 12 24 0 4 1536
22.05 64 1.4112 84.672 1 1.411 60 30 2 3840 960 4 21.168 256 5644.8 15 16 0 4 1411.2
22.05 128 2.8224 84.672 1 2.822 30 30 1 3840 960 4 21.168 256 5644.8 15 16 0 4 1411.2
22.05 192 4.2336 84.672 3 1.411 60 30 2 3840 960 4 21.168 256 5644.8 15 16 0 4 1411.2
22.05 256 5.6448 84.672 2 2.822 30 30 1 3840 960 4 21.168 256 5644.8 15 16 0 4 1411.2
22.05 384 8.4672 84.672 3 2.822 30 30 1 3840 960 4 21.168 256 5644.8 15 16 0 4 1411.2
22.05 512 11.2896 84.672 2 5.645 15 15 1 3840 960 4 21.168 256 5644.8 15 16 0 4 1411.2
22.05 768 16.9344 84.672 3 5.645 15 15 1 3840 960 4 21.168 256 5644.8 15 16 0 4 1411.2
22.05 1024 22.5792 84.672 4 5.645 15 15 1 3840 960 4 21.168 256 5644.8 15 16 0 4 1411.2
22.05 1152 25.4016 84.672 9 2.822 30 30 1 3840 960 4 21.168 256 5644.8 15 16 0 4 1411.2
22.05 1536 33.8688 84.672 8 4.234 20 20 1 3840 960 4 21.168 256 5644.8 15 16 0 4 1411.2
22.05 2048 45.1584 84.672 8 5.645 15 15 1 3840 960 4 21.168 256 5644.8 15 16 0 4 1411.2
32 32 1.024 73.728 1 1.024 72 36 2 2304 768 3 24.576 192 6144 12 12 0 4 1536
32 48 1.536 73.728 1 1.536 48 12 4 2304 768 3 24.576 192 6144 12 12 0 4 1536
32 64 2.048 73.728 1 2.048 36 18 2 2304 768 3 24.576 192 6144 12 12 0 4 1536
32 128 4.096 73.728 2 2.048 36 36 1 2304 768 3 24.576 192 6144 12 12 0 4 1536
32 192 6.144 73.728 3 2.048 36 36 1 2304 768 3 24.576 192 6144 12 12 0 4 1536
32 256 8.192 73.728 4 2.048 36 36 1 2304 768 3 24.576 192 6144 12 12 0 4 1536
32 384 12.288 73.728 6 2.048 36 36 1 2304 768 3 24.576 192 6144 12 12 0 4 1536
32 512 16.384 73.728 8 2.048 36 36 1 2304 768 3 24.576 192 6144 12 12 0 4 1536
32 768 24.576 73.728 6 4.096 18 18 1 2304 768 3 24.576 192 6144 12 12 0 4 1536
32 1024 32.768 73.728 8 4.096 18 18 1 2304 768 3 24.576 192 6144 12 12 0 4 1536
32 1152 36.864 73.728 9 4.096 18 18 1 2304 768 3 24.576 192 6144 12 12 0 4 1536
32 1536 49.152 73.728 12 4.096 18 18 1 2304 768 3 24.576 192 6144 12 12 0 4 1536
44.1 32 1.4112 84.672 1 1.411 60 30 2 1920 960 2 42.336 128 5644.8 15 8 0 4 1411.2
44.1 48 2.1168 84.672 1 2.117 40 10 4 1920 960 2 42.336 128 5644.8 15 8 0 4 1411.2
44.1 64 2.8224 84.672 1 2.822 30 15 2 1920 960 2 42.336 128 5644.8 15 8 0 4 1411.2
44.1 128 5.6448 84.672 1 5.645 15 15 1 1920 960 2 42.336 128 5644.8 15 8 0 4 1411.2
44.1 192 8.4672 84.672 2 4.234 20 20 1 1920 960 2 42.336 128 5644.8 15 8 0 4 1411.2
44.1 256 11.2896 84.672 2 5.645 15 15 1 1920 960 2 42.336 128 5644.8 15 8 0 4 1411.2
44.1 384 16.9344 84.672 3 5.645 15 15 1 1920 960 2 42.336 128 5644.8 15 8 0 4 1411.2
44.1 512 22.5792 84.672 4 5.645 15 15 1 1920 960 2 42.336 128 5644.8 15 8 0 4 1411.2
44.1 768 33.8688 84.672 6 5.645 15 15 1 1920 960 2 42.336 128 5644.8 15 8 0 4 1411.2
44.1 1024 45.1584 84.672 8 5.645 15 15 1 1920 960 2 42.336 128 5644.8 15 8 0 4 1411.2
48 32 1.536 73.728 1 1.536 48 24 2 1536 768 2 36.864 128 6144 12 8 0 4 1536
48 48 2.304 73.728 1 2.304 32 8 4 1536 768 2 36.864 128 6144 12 8 0 4 1536
48 64 3.072 73.728 1 3.072 24 12 2 1536 768 2 36.864 128 6144 12 8 0 4 1536
48 128 6.144 73.728 2 3.072 24 24 1 1536 768 2 36.864 128 6144 12 8 0 4 1536
48 192 9.216 73.728 3 3.072 24 24 1 1536 768 2 36.864 128 6144 12 8 0 4 1536
48 256 12.288 73.728 4 3.072 24 24 1 1536 768 2 36.864 128 6144 12 8 0 4 1536
48 384 18.432 73.728 6 3.072 24 24 1 1536 768 2 36.864 128 6144 12 8 0 4 1536
48 512 24.576 73.728 4 6.144 12 12 1 1536 768 2 36.864 128 6144 12 8 0 4 1536
48 768 36.864 73.728 6 6.144 12 12 1 1536 768 2 36.864 128 6144 12 8 0 4 1536
48 1024 49.152 73.728 8 6.144 12 12 1 1536 768 2 36.864 128 6144 12 8 0 4 1536
96 32 3.072 73.728 2 1.536 48 24 2 768 384 2 36.864 64 6144 12 4 0 4 1536
96 48 4.608 73.728 3 1.536 48 24 2 768 384 2 36.864 64 6144 12 4 0 4 1536
96 64 6.144 73.728 2 3.072 24 12 2 768 384 2 36.864 64 6144 12 4 0 4 1536
96 128 12.288 73.728 4 3.072 24 24 1 768 384 2 36.864 64 6144 12 4 0 4 1536
96 192 18.432 73.728 6 3.072 24 24 1 768 384 2 36.864 64 6144 12 4 0 4 1536
96 256 24.576 73.728 8 3.072 24 24 1 768 384 2 36.864 64 6144 12 4 0 4 1536
96 384 36.864 73.728 6 6.144 12 12 1 768 384 2 36.864 64 6144 12 4 0 4 1536
96 512 49.152 73.728 8 6.144 12 12 1 768 384 2 36.864 64 6144 12 4 0 4 1536
192 32 6.144 73.728 2 3.072 24 12 2 384 192 2 36.864 32 6144 12 2 0 4 1536
192 48 9.216 73.728 3 3.072 24 12 2 384 192 2 36.864 32 6144 12 2 0 4 1536
192 64 12.288 73.728 4 3.072 24 12 2 384 192 2 36.864 32 6144 12 2 0 4 1536
192 128 24.576 73.728 8 3.072 24 24 1 384 192 2 36.864 32 6144 12 2 0 4 1536
192 192 36.864 73.728 6 6.144 12 12 1 384 192 2 36.864 32 6144 12 2 0 4 1536
192 256 49.152 73.728 8 6.144 12 12 1 384 192 2 36.864 32 6144 12 2 0 4 1536
384 32 12.288 73.728 2 6.144 12 6 2 192 96 2 36.864 16 6144 12 1 0 4 1536
384 48 18.432 73.728 3 6.144 12 6 2 192 96 2 36.864 16 6144 12 1 0 4 1536
384 64 24.576 73.728 4 6.144 12 6 2 192 96 2 36.864 16 6144 12 1 0 4 1536
384 128 49.152 73.728 8 6.144 12 12 1 192 96 2 36.864 16 6144 12 1 0 4 1536

Table 124. Recommended Clock Divider Settings for SCK as Master Clock

fS (kHz) RSCK SCK (MHz) DSP fS NMAC DSP CLK (MHz) MOD fS MOD f (kHz) NDAC DOSR NCP CP f (kHz)
8 256 2.048 256 1 2.048 256 2048 1 16 2 1024
8 384 3.072 384 1 3.072 384 3072 1 24 2 1536
8 512 4.096 512 1 4.096 512 4096 1 32 2 2048
8 768 6.144 768 1 6.144 768 6144 1 48 4 1536
8 1024 8.192 1024 1 8.192 512 4096 2 32 2 2048
8 1152 9.216 1152 1 9.216 576 4608 2 36 4 1152
8 1536 12.288 1536 1 12.288 768 6144 2 48 4 1536
8 2048 16.384 2048 1 16.384 512 4096 4 32 2 2048
8 3072 24.576 3072 1 24.576 768 6144 4 48 4 1536
11.025 256 2.8224 256 1 2.822 256 2822.4 1 16 2 1411.2
11.025 384 4.2336 384 1 4.234 384 4233.6 1 24 4 1058.4
11.025 1152 12.7008 1152 1 12.701 384 4233.6 3 24 4 1058.4
11.025 1536 16.9344 1536 1 16.934 512 5644.8 3 32 4 1411.2
11.025 2048 22.5792 2048 1 22.579 512 5644.8 4 32 4 1411.2
11.025 3072 33.8688 3072 1 33.869 512 5644.8 6 32 4 1411.2
16 256 4.096 256 1 4.096 256 4096 1 16 2 2048
16 384 6.144 384 1 6.144 384 6144 1 24 4 1536
16 512 8.192 512 1 8.192 256 4096 2 16 2 2048
16 768 12.288 768 1 12.288 384 6144 2 24 4 1536
16 1152 18.432 1152 1 18.432 288 4608 4 18 4 1152
16 1536 24.576 1536 1 24.576 384 6144 4 24 4 1536
16 2048 32.768 2048 1 32.768 256 4096 8 16 2 2048
16 3072 49.152 3072 1 49.152 384 6144 8 24 4 1536
22.05 256 5.6448 256 1 5.645 256 5644.8 1 16 4 1411.2
22.05 384 8.4672 384 1 8.467 192 4233.6 2 12 4 1058.4
22.05 512 11.2896 512 1 11.29 256 5644.8 2 16 4 1411.2
22.05 768 16.9344 768 1 16.934 256 5644.8 3 16 4 1411.2
22.05 1024 22.5792 1024 1 22.579 256 5644.8 4 16 4 1411.2
22.05 1152 25.4016 1152 1 25.402 192 4233.6 6 12 4 1058.4
22.05 1536 33.8688 1536 1 33.869 256 5644.8 6 16 4 1411.2
22.05 2048 45.1584 2048 1 45.158 256 5644.8 8 16 4 1411.2
32 256 8.192 256 1 8.192 128 4096 2 8 2 2048
32 384 12.288 384 1 12.288 128 4096 3 8 2 2048
32 512 16.384 512 1 16.384 128 4096 4 8 2 2048
32 768 24.576 768 1 24.576 128 4096 6 8 2 2048
32 1024 32.768 1024 1 32.768 128 4096 8 8 2 2048
32 1152 36.864 1152 1 36.864 128 4096 9 8 4 1024
32 1536 49.152 1536 1 49.152 128 4096 12 8 4 1024
44.1 256 11.2896 256 1 11.29 128 5644.8 2 8 4 1411.2
44.1 384 16.9344 384 1 16.934 128 5644.8 3 8 4 1411.2
44.1 512 22.5792 512 1 22.579 128 5644.8 4 8 4 1411.2
44.1 768 33.8688 768 1 33.869 128 5644.8 6 8 4 1411.2
44.1 1024 45.1584 1024 1 45.158 128 5644.8 8 8 4 1411.2
48 256 12.288 256 1 12.288 128 6144 2 8 4 1536
48 384 18.432 384 1 18.432 128 6144 3 8 4 1536
48 512 24.576 512 1 24.576 128 6144 4 8 4 1536
48 768 36.864 768 1 36.864 128 6144 6 8 4 1536
48 1024 49.152 1024 1 49.152 128 6144 8 8 4 1536
96 192 18.432 192 1 18.432 48 4608 4 3 6 768
96 256 24.576 256 1 24.576 64 6144 4 4 4 1536
96 384 36.864 384 1 36.864 64 6144 6 4 4 1536
96 512 49.152 512 1 49.152 64 6144 8 4 4 1536
192 128 24.576 128 1 24.576 32 6144 4 2 4 1536
192 192 36.864 192 1 36.864 32 6144 6 2 4 1536
192 256 49.152 256 1 49.152 32 6144 8 2 4 1536
384 64 24.576 64 1 24.576 16 6144 4 1 4 1536
384 128 49.152 128 1 49.152 16 6144 8 1 4 1536
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