In addition to supporting analog microphones, the device also interfaces to digital pulse-density-modulation (PDM) microphones and uses high-order and high-performance decimation filters to generate pulse code modulation (PCM) output data that can be transmitted on the audio serial interface to the host. The device supports up to four digital microphone recording channels. If the second channel analog microphone is not used in the system, then the analog input pins (IN2P and IN2M) can be repurposed as the GPI1 and GPO1 pins, respectively, and can be configured for the PDMDIN1 and PDMCLK clocks for digital PDM microphone recording. GPIO1 or GPI2 (multiplexed with MICBIAS) can be used as PDMDIN2 to enable four-channel PDM microphone recording. If two-channel analog input recording is needed, MICBIAS (configured as GPI2) and GPIO1 can be used as PDMDIN and PDMCLK, respectively, to enable two-channel DMIC recording along with two-channel AIN recording. The device can support a total of four channels at the input (analog and digital).

The device internally generates PDMCLK with a programmable frequency of either 6.144 MHz, 3.072 MHz, 1.536 MHz, or 768 kHz (for output data sample rates in multiples or submultiples of 48 kHz) or 5.6448 MHz, 2.8224 MHz, 1.4112 MHz, or 705.6 kHz (for output data sample rates in multiples or submultiples of 44.1 kHz) using the PDMCLK_DIV[1:0] (P0_R31_D[1:0]) register bits. PDMCLK can be routed on the GPO1 and GPIO1 pins. This clock can be connected to the external digital microphone device. Figure 8-64 shows a connection diagram of the digital PDM microphones.

The single-bit output of the external digital microphone device can be connected to the GPIx pin. This single data line can be shared by two digital microphones to place their data on the opposite edge of PDMCLK. Internally, the device latches the steady value of the data on either the rising or falling edge of PDMCLK based on the configuration register bits set in P0_R32_D[7:4]. Figure 8-65 shows the digital PDM microphone interface timing diagram.

Figure 8-65 Digital PDM Microphone Protocol Timing Diagram

When the digital microphone is used for recording, the analog blocks of the respective ADC channel are powered down and bypassed for power efficiency. Use the CH1_INSRC[1:0] (P0_R60_D[6:5]) and CH2_INSRC[1:0] (P0_R65_D[6:5]) register bits to select the analog microphone or digital microphone for channel 1 to channel 2. Channel 3 and channel 4 support only the digital microphone interface.