ZHCSPD6A April 2022 – August 2022 PCM6120-Q1
PRODUCTION DATA
Digital audio data flows between the host processor and the PCM6120-Q1 on the digital audio serial interface (ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for I2S or left-justified protocols format, programmable data length options, very flexible master-slave configurability for bus clock lines, and the ability to communicate with multiple devices within a system directly.
The bus protocol TDM, I2S, or left-justified (LJ) format can be selected by using the ASI_FORMAT[1:0] (P0_R7_D[7:6]) register bits. As shown in Table 8-2 and Table 8-3, these modes are all most significant bit (MSB)-first, pulse code modulation (PCM) data format, with the output channel data word-length programmable as 16, 20, 24, or 32 bits by configuring the ASI_WLEN[1:0] (P0_R7_D[5:4]) register bits.
| P0_R7_D[7:6] : ASI_FORMAT[1:0] | AUDIO SERIAL INTERFACE FORMAT |
|---|---|
| 00 (default) | Time division multiplexing (TDM) mode |
| 01 | Inter IC sound (I2S) mode |
| 10 | Left-justified (LJ) mode |
| 11 | Reserved (do not use this setting) |
| P0_R7_D[5:4] : ASI_WLEN[1:0] | AUDIO OUTPUT CHANNEL DATA WORD-LENGTH |
|---|---|
| 00 | Output channel data word-length set to 16 bits |
| 01 | Output channel data word-length set to 20 bits |
| 10 | Output channel data word-length set to 24 bits |
| 11 (default) | Output channel data word-length set to 32 bits |
The frame sync pin, FSYNC, is used to define the beginning of a frame and has the same frequency as the output data sample rates. The bit clock pin, BCLK, is used to clock out the digital audio data across the serial bus. The number of bit-clock cycles in a frame must accommodate all active output channels with the programmed data word length.
A frame consists of multiple time-division channel slots (up to 64) on the audio bus. This allows for either a single device or multiple PCM6120-Q1 devices sharing the same bus. The device supports up to four output channels that can be configured to place their audio data on bus slot 0 to slot 63. Table 8-4 lists the output channel slot configuration settings. In I2S and LJ mode, the slots are divided into two sets, left-channel slots and right-channel slots, as described in Section 8.3.1.2.2 and Section 8.3.1.2.3.
| P0_R11_D[5:0] : CH1_SLOT[5:0] | OUTPUT CHANNEL 1 SLOT ASSIGNMENT |
|---|---|
| 00 0000 = 0d (default) | Slot 0 for TDM or left slot 0 for I2S, LJ. |
| 00 0001 = 1d | Slot 1 for TDM or left slot 1 for I2S, LJ. |
| … | … |
| 01 1111 = 31d | Slot 31 for TDM or left slot 31 for I2S, LJ. |
| 10 0000 = 32d | Slot 32 for TDM or right slot 0 for I2S, LJ. |
| … | … |
| 11 1110 = 62d | Slot 62 for TDM or right slot 30 for I2S, LJ. |
| 11 1111 = 63d | Slot 63 for TDM or right slot 31 for I2S, LJ. |
Similarly, the slot assignment setting for output channel 2 to channel 8 can be done using the CH2_SLOT (P0_R12) to CH8_SLOT (P0_R18) registers, respectively.
The slot word length is the same as the output channel data word length set for the device. The output channel data word length must be set to the same value for all PCM6120-Q1 devices if all devices share the same ASI bus in a system. The maximum number of slots possible for the ASI bus in a system is limited by the available bus bandwidth, which depends upon the BCLK frequency, output data sample rate used, and the channel data word length configured.
The device also includes a feature that offsets the start of the slot data transfer with respect to the frame sync by up to 31 cycles of the bit clock. Table 8-5 lists the programmable offset configuration settings.
| P0_R8_D[4:0] : TX_OFFSET[4:0] | PROGRAMMABLE OFFSET SETTING FOR SLOT DATA TRANSMISSION START |
|---|---|
| 0 0000 = 0d (default) | The device follows the standard protocol timing without any offset. |
| 0 0001 = 1d | Slot start is offset by one BCLK cycle, as
compared to standard protocol timing. For I2S or LJ, the left and right slot start is offset by one BCLK cycle, as compared to standard protocol timing. |
| ...... | ...... |
| 1 1110 = 30d | Slot start is offset by 30 BCLK cycles, as
compared to standard protocol timing. For I2S or LJ, the left and right slot start is offset by 30 BCLK cycles, as compared to standard protocol timing. |
| 1 1111 = 31d | Slot start is offset by 31 BCLK cycles, as
compared to standard protocol timing. For I2S or LJ, the left and right slot start is offset by 31 BCLK cycles, as compared to standard protocol timing. |
The device also features the ability to invert the polarity of the frame sync pin, FSYNC, used to transfer the audio data as compared to the default FSYNC polarity used in standard protocol timing. This feature can be set using the FSYNC_POL (P0_R7_D3) register bit. Similarly, the device can invert the polarity of the bit clock pin, BCLK, which can be set using the BCLK_POL (P0_R7_D2) register bit.