8.1 Overview

The PCM6xx0-Q1 are a scalable family of devices that consist of high-performance, low-power, flexible, multichannel, audio analog-to-digital converters (ADCs) with extensive feature integration. These devices are intended for automotive applications such as vehicle cabin active noise cancellation, hands-free in-vehicle communication, emergency call, and multimedia applications. The high dynamic range of these devices enables far-field audio recording with high fidelity. These devices integrate a host of features that reduce cost, board space, and power consumption in space-constrained automotive sub-system designs. Package, performance, and device-compatible configuration registers make this family of devices well suited for scalable system designs.

The PCM6xx0-Q1 consist of the following blocks:

• Multichannel, multibit, high-performance delta-sigma (ΔΣ) ADCs
• Configurable single-ended or differential audio inputs with high voltage signal swing
• High-voltage, low-noise programmable microphone bias output
• Highly flexible, comprehensive input fault diagnostic
• Automatic gain controller (AGC)
• Programmable decimation filters with linear-phase or low-latency filter
• Programmable channel gain, volume control, and biquad filters for each channel
• Programmable phase and gain calibration with fine resolution for each channel
• Programmable high-pass filter (HPF) and digital channel mixer
• Integrated low-jitter, phase-locked loop (PLL) supporting a wide range of system clocks
• Integrated digital and analog voltage regulators to support single-supply operation

Communication to the PCM6xx0-Q1 for configuring the control registers is supported using an I²C or SPI interface. The device supports a highly flexible audio serial interface [time-division multiplexing (TDM), I²S, or left-justified (LJ)] to transmit audio data seamlessly in the system across devices.

The device can support multiple devices by sharing the common I²C and TDM buses across devices. Moreover, the device includes a daisy-chain feature and a secondary audio serial output data pin. These features relax the shared TDM bus timing requirements and board design complexities when operating multiple devices for applications requiring high audio data bandwidth.

Table 1 lists the reference abbreviations used throughout this document to registers that control the device.