9.2.1.2 Detailed Design Procedure

This section describes the necessary steps to configure the PCM6240-Q1 for this specific application. The following steps give a sequence of items that must be executed in the time between powering the device up and reading data from the device or transitioning from one mode to other mode of operation.

1. Apply Power to Device:
   1. Power up the IOVDD, AVDD, and BSTVDD power supplies, keeping the SHDNZ pin voltage low
   2. The device now goes into hardware shutdown mode (ultra-low-power mode < 1 µA)
2. Transition From Hardware Shutdown Mode to Sleep Mode (or Software Shutdown Mode):
   1. Release SHDNZ only when the IOVDD, AVDD, and BSTVDD power supplies settle to steady-state operating voltage
   2. Wait for at least 1 ms to allow the device to initialize the internal registers
   3. The device now goes into sleep mode (low-power mode < 20 µA)
3. Transition From Sleep Mode to Active Mode Whenever Required for the Record Operation:
   1. Wake-up the device by writing P0_R2 to disable sleep mode
   2. Wait for at least 1ms to allow the device internal wake-up sequence to complete
   3. Override the default configuration registers or programmable coefficients value as required (optional)
   4. Enable all desired input channels by writing P0_R115
   5. Enable all desired audio serial interface output channels by writing P0_R116
   6. Power-up the ADC, MICBIAS, and PLL by writing P0_R117
   7. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio

   This specific step can be done at any point in the sequence after step a

   See the Phase-Locked Loop (PLL) and Clock Generation section for the supported sample rates and the BCLK to FSYNC ratio

   8. The device recording data are now sent to the host processor via the TDM audio serial data bus
   9. Wait for at least 10 ms to allow the MICBIAS to power up
   10. Enable the fault diagnostics for all desired input channels by writing P0_R100
4. Transition From Active Mode to Sleep Mode (Again) as Required in the System Low Power:
   1. Disable the fault diagnostics for all desired input channels by writing P0_R100
   2. Go to sleep mode by writing P0_R2 to enable sleep mode
   3. Wait at least 20 ms to allow the volume to gradually ramp down and for all blocks to power down
   4. Read P0_R119 to check the device shutdown and sleep mode status
   5. If the device P0_R119_D7 status bit is 1'b1, then stop FSYNC and BCLK in the system
   6. The device now goes into sleep mode (low-power mode < 20 µA) and retains all register values
5. Transition From Sleep Mode to Active Mode (Again) as Required for the Record Operation:
   1. Wake-up the device by writing P0_R2 to disable sleep mode
   2. Wait for at least 1 ms to allow the device internal wake-up sequence to complete
   3. Apply FSYNC and BCLK with the desired output sample rates and BCLK to FSYNC ratio
   4. The device recording data are now sent to the host processor via the TDM audio serial data bus
   5. Wait for at least 10 ms to allow the MICBIAS to power up
   6. Enable the fault diagnostics for all desired input channels by writing P0_R100
6. Repeat Step 4 and Step 5 as Required for Mode Transitions
7. Assert the SHDNZ Pin Low to Enter Hardware Shutdown Mode (Again) at Any Time
8. Follow Step 2 Onwards to Exit Hardware Shutdown Mode (Again)