The power-supply sequence between the IOVDD and AVDD rails can be applied in any order. However, keep the SHDNZ pin low until the IOVDD supply voltage settles to a stable and supported operating voltage range. After the IOVDD and AVDD supplies are stable, set the SHDNZ pin high to initialize the device. BSTVDD (or HVDD for the PCM63x0-Q1) can be either applied along with AVDD or later but before turning on the MICBIAS. Figure 231 shows the power supply sequencing requirements.

Figure 231. Power-Supply Sequencing Requirement

For the supply power-up requirement, t₁ and t₂ must be at least 100 µs. For the supply power-down requirement, t₃ and t₄ must be at least 10 ms. This time allows the device to ramp down the volume on the record data, and power down the analog and digital blocks, and lastly put the device into hardware shutdown mode. The device can also be immediately put into hardware shutdown mode from active mode if SHDNZ_CFG[1:0] is set to 2'b00 using the P0_R5_D[3:2] bits. In that case, t₃ and t₄ are required to be at least 100 µs.

Make sure that the supply ramp rate is faster than 1 V/µs and that the wait time between a power-down and a power-up event is at least 100 ms.

After the releasing SHDNZ, or after a software reset, delay any additional I²C or SPI transactions to the device for at least 2 ms to allow the device to initialize the internal registers. See the Device Functional Modes section to operate the device in various modes after the device power supplies are settled to the recommended operating voltage levels.