ZHCSIM2D June 2010 – August 2021 PCM9211
PRODUCTION DATA
The DIT can accept a 128fS, 256fS, or 512fS system clock. The clock ratio selection is set by using the Register TXSCK[2:0]. A 216-kHz sampling frequency is supported by using the 128fS or 256fS system clock ratio. A 108-kHz sampling frequency can be supported up to a 512fS clock ratio.
I2S, 24-bit left-justified, 24-bit right-justified, and 16-bit right-justified serial audio interface formats can be used. Only slave mode is supported. Table 7-10 shows the relationship between typical audio sampling frequencies and the respective BCK and SCK frequencies
| LRCK | BCK | SCK | ||
|---|---|---|---|---|
| fS | 64fS | 128fS | 256fS | 512fS |
| 8 kHz | 0.512 MHz | 1.024MHz | 2.048 MHz | 4.096 MHz |
| 11.025 kHz | 0.7056 MHz | 1.4112 MHz | 2.8224 MHz | 5.6448 MHz |
| 12 kHz | 0.768 MHz | 1.536 MHz | 3.072 MHz | 6.144 MHz |
| 16 kHz | 1.024 MHz | 2.048 MHz | 4.096 MHz | 8.192 MHz |
| 22.05 kHz | 1.4112 MHz | 2.8224 MHz | 5.6448 MHz | 11.2896 MHz |
| 24 kHz | 1.536 MHz | 3.072 MHz | 6.144 MHz | 12.288 MHz |
| 32 kHz | 2.048 MHz | 4.096 MHz | 8.192 MHz | 16.384 MHz |
| 44.1 kHz | 2.8224 MHz | 5.6448 MHz | 11.2896 MHz | 22.5792 MHz |
| 48 kHz | 3.072 MHz | 6.144 MHz | 12.288 MHz | 24.576 MHz |
| 64 kHz | 4.096 MHz | 8.192 MHz | 16.384 MHz | 32.768 MHz |
| 88.2 kHz | 5.6448 MHz | 11.2896 MHz | 22.5792 MHz | 45.1584 MHz |
| 96 kHz | 6.144 MHz | 12.288 MHz | 24.576 MHz | 49.152 MHz |
| 128 kHz | 8.192 MHz | 16.384 MHz | 32.768 MHz | N/A |
| 176.4 kHz | 11.2896 MHz | 22.5792 MHz | 45.1584 MHz | N/A |
| 192 kHz | 12.288 MHz | 24.576 MHz | 49.152 MHz | N/A |